25.8.4 Status
| Name: | STATUS |
| Offset: | 0x0C |
| Reset: | x,y initially determined from NVM User Row after reset |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ULPVREFRDY | VCORERDY | VREGRDY | |||||||
| Access | R | R | R | ||||||
| Reset | x | 1 | 1 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| B33SRDY | BOD33DET | BOD33RDY | |||||||
| Access | R | R | R | ||||||
| Reset | 0 | 0 | y |
Bit 12 – ULPVREFRDY Low Power Voltage Reference Ready
| Value | Description |
|---|---|
| 0 | The ULPVREF voltage is not as expected. |
| 1 | The ULPVREF voltage is the target voltage. |
Bit 10 – VCORERDY VDDCORE Voltage Ready
| Value | Description |
|---|---|
| 0 | The VDDCORE voltage is not as expected. |
| 1 | The VDDCORE voltage is the target voltage. |
Bit 8 – VREGRDY Voltage Regulator Ready
| Value | Description |
|---|---|
| 0 | The selected voltage regulator in VREG.SEL is not ready. |
| 1 | The voltage regulator selected in VREG.SEL is ready and the core domain is supplied by this voltage regulator. |
Bit 2 – B33SRDY BOD33 Synchronization Ready
| Value | Description |
|---|---|
| 0 | BOD33 synchronization is ongoing. |
| 1 | BOD33 synchronization is complete. |
Bit 1 – BOD33DET BOD33 Detection
| Value | Description |
|---|---|
| 0 | No BOD33 detection. |
| 1 | BOD33 has detected that the I/O power supply is going below the BOD33 reference value. |
Bit 0 – BOD33RDY BOD33 Ready
The BOD33 can be enabled at start-up from NVM User Row.
The state of this bit is only applicable in BOD33 continuous mode. In sampling mode, this bit is never set.
| Value | Description |
|---|---|
| 0 | BOD33 is not ready. |
| 1 | BOD33 is ready. |