25.8.1 Interrupt Enable Clear

This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET).
Name: INTENCLR
Offset: 0x00
Reset: 0x00000000
Property: PAC Write-Protection

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
     ULPVREFRDYVCORERDY VREGRDY 
Access R/WR/WR/W 
Reset 000 
Bit 76543210 
      B33SRDYBOD33DETBOD33RDY 
Access R/WR/WR/W 
Reset 000 

Bit 11 – ULPVREFRDY Low Power Voltage Reference Ready Interrupt Enable

Writing a '0' to this bit has no effect.

The ULPVREFRDY bit will clear on a zero-to-one transition of the Low Power Voltage Reference Ready bit in the Status register (STATUS.ULPVREFRDY).

ValueDescription
0 The Low Power Ready interrupt is disabled.
1 The Low Power Ready interrupt is enabled and an interrupt request will be generated when the ULPVREFRDY Interrupt Flag is set.

Bit 10 – VCORERDY VDDCORE Voltage Ready Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will clear the VDDCORE Ready Interrupt Enable bit, which disables the VDDCORE Ready interrupt.

ValueDescription
0 The VDDCORE Ready interrupt is disabled.
1 The VDDCORE Ready interrupt is enabled and an interrupt request will be generated when the VCORERDY Interrupt Flag is set.

Bit 8 – VREGRDY Voltage Regulator Ready Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will clear the Voltage Regulator Ready Interrupt Enable bit, which disables the Voltage Regulator Ready interrupt.

ValueDescription
0 The Voltage Regulator Ready interrupt is disabled.
1 The Voltage Regulator Ready interrupt is enabled and an interrupt request will be generated when the Voltage Regulator Ready Interrupt Flag is set.

Bit 2 – B33SRDY  BOD33 Synchronization Ready Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will clear the BOD33 Synchronization Ready Interrupt Enable bit, which disables the BOD33 Synchronization Ready interrupt.

ValueDescription
0 The BOD33 Synchronization Ready interrupt is disabled.
1 The BOD33 Synchronization Ready interrupt is enabled, and an interrupt request will be generated when the BOD33 Synchronization Ready Interrupt flag is set.

Bit 1 – BOD33DET  BOD33 Detection Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will clear the BOD33 Detection Interrupt Enable bit, which disables the BOD33 Detection interrupt.

ValueDescription
0 The BOD33 Detection interrupt is disabled.
1 The BOD33 Detection interrupt is enabled, and an interrupt request will be generated when the BOD33 Detection Interrupt flag is set.

Bit 0 – BOD33RDY  BOD33 Ready Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will clear the BOD33 Ready Interrupt Enable bit, which disables the BOD33 Ready interrupt.

ValueDescription
0 The BOD33 Ready interrupt is disabled.
1 The BOD33 Ready interrupt is enabled, and an interrupt request will be generated when the BOD33 Ready Interrupt flag is set.