13.2.7 Cortex-M23 Test Target Instructions
Software may check the privilege state of a memory location by using the Cortex-M23 Test Target instructions: TT, TTT, TTA, and TTAT.
The memory location is referenced using the Cortex-M23 IREGION bitfield, which specifies the IDAU region number (see the ARMv8-M Architecture Reference Manual for more information).
| Memory Region | IDAU Region Number for TTx Instructions (IREGION bits) |
|---|---|
| Secure Flash (BOOT region) | 0x01 |
| Non-Secure Callable Flash (BOOT region) | 0x02 |
| Non-Secure Flash (BOOT region) | 0x03 |
| Secure Flash (APPLICATION region) | 0x04 |
| Non-Secure Callable Flash (APPLICATION region) | 0x05 |
| Non-Secure Flash (APPLICATION region) | 0x06 |
| Secure Data Flash | 0x07 |
| Non-Secure Data Flash | 0x08 |
| NVM User Rows | 0x00 (invalid) |
| Boot ROM | 0x09 |
| Secure SRAM | 0x0A |
| Non-Secure SRAM | 0x0B |
| Peripherals | 0x00 (invalid) |
| IOBUS | 0x00 (invalid) |
| Others (Reserved, Undefined...) | 0x00 (invalid) |