41.8.5 Interrupt Enable Clear

This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register.
Name: INTENCLR
Offset: 0x04
Reset: 0x00
Property: PAC Write-Protection

Bit 76543210 
      WINMONOVERRUNRESRDY 
Access R/WR/WR/W 
Reset 000 

Bit 2 – WINMON Window Monitor Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will clear the Window Monitor Interrupt Enable bit, which disables the corresponding interrupt request.

ValueDescription
0 The window monitor interrupt is disabled.
1 The window monitor interrupt is enabled, and an interrupt request will be generated when the Window Monitor interrupt flag is set.

Bit 1 – OVERRUN Overrun Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will clear the Overrun Interrupt Enable bit, which disables the corresponding interrupt request.

ValueDescription
0 The Overrun interrupt is disabled.
1 The Overrun interrupt is enabled, and an interrupt request will be generated when the Overrun interrupt flag is set.

Bit 0 – RESRDY Result Ready Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will clear the Result Ready Interrupt Enable bit, which disables the corresponding interrupt request.

ValueDescription
0 The Result Ready interrupt is disabled.
1 The Result Ready interrupt is enabled, and an interrupt request will be generated when the Result Ready interrupt flag is set.