41.8.12 Sampling Time Control

Name: SAMPCTRL
Offset: 0x0D
Reset: 0x00
Property: PAC Write-Protection, Write-Synchronized

Bit 76543210 
 OFFCOMP SAMPLEN[5:0] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 

Bit 7 – OFFCOMP Comparator Offset Compensation Enable

Setting this bit enables the offset compensation for each sampling period to ensure low offset and immunity to temperature or voltage drift. ADC sampling time is fixed to 4 ADC Clock cycles when OFFCOMP = 1.

Bits 5:0 – SAMPLEN[5:0] Sampling Time Length

These bits control the ADC sample time (Ts) in number of ADC Clock Period (CLK_ADC), depending of the prescaler value, thus controlling the ADC input impedance. Sampling time is set according to the equation:

T S = ( SAMPLEN + 1 ) ( CLK ADC )

SAMPLEN is only available when OFFCOMP=0.

Note: Refer to the ADC Electrical Characteristics for TS computation.