19.14.4 TMRxGATE

Timer Gate Source Selection Register

Name:	TMRxGATE
Address:	0x210,0x216,0x21C


Bit	7	6	5	4	3	2	1	0
				GSS[4:0]
Access				R/W	R/W	R/W	R/W	R/W
Reset				0	0	0	0	0

Bits 4:0 – GSS[4:0] Timer Gate Source Selection bits

Table 19-3. Timer Gate Sources
GSS	Gate Source
GSS	Timer1	Timer3	Timer5
`11111-11001`	Reserved	Reserved	Reserved
`11000`	SMT2_overflow	SMT2_overflow	SMT2_overflow
`10111`	CCP5_out	CCP5_out	CCP5_out
`10110`	CLC4_out	CLC4_out	CLC4_out
`10101`	CLC3_out	CLC3_out	CLC3_out
`10100`	CLC2_out	CLC2_out	CLC2_out
`10011`	CLC1_out	CLC1_out	CLC1_out
`10010`	ZCD1_output	ZCD1_output	ZCD1_output
`10001`	C2OUT_sync	C2OUT_sync	C2OUT_sync
`10000`	C1OUT_sync	C1OUT_sync	C1OUT_sync
`01111`	NCO1_out	NCO1_out	NCO1_out
`01110`	PWM7_out	PWM7_out	PWM7_out
`01101`	PWM6_out	PWM6_out	PWM6_out
`01100`	CCP4_out	CCP4_out	CCP4_out
`01011`	CCP3_out	CCP3_out	CCP3_out
`01010`	CCP2_out	CCP2_out	CCP2_out
`01001`	CCP1_out	CCP1_out	CCP1_out
`01000`	SMT1_overflow	SMT1_overflow	SMT1_overflow
`00111`	TMR6_postscaled output	TMR6_postscaled output	TMR6_postscaled output
`00110`	Timer5 overflow output	Timer5 overflow output	Reserved
`00101`	TMR4_postscaled output	TMR4_postscaled output	TMR4_postscaled output
`00100`	Timer3 overflow output	Reserved	Timer3 overflow output
`00011`	TMR2_postscaled output	TMR2_postscaled output	TMR2_postscaled output
`00010`	Reserved	Timer1 overflow output	Timer1 overflow output
`00001`	Timer0 overflow output	Timer0 overflow output	Timer0 overflow output
`00000`	T1GPPS	T3GPPS	T5GPPS

Reset States:

POR/BOR = 00000

All Other Resets = uuuuu

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