6.6.3 NVMCON1

Nonvolatile Memory Control 1 Register

Note:

Bit is undefined while WR = 1 (during the EEPROM write operation it may be ‘0’ or ‘1’).
Bit must be cleared by software; hardware will not clear this bit.
Bit may be written to ‘1’ by the user to implement test sequences.
This bit can only be set by following the sequence described in the “NVM Unlock Sequence” section.
Operations are self-timed and the WR bit is cleared by hardware when complete.
Once a write operation is initiated, setting this bit to zero will have no effect.
Reading from EEPROM loads only NVMDATL.

Name:	NVMCON1
Address:	0x81E


Bit	7	6	5	4	3	2	1	0
		NVMREGS	LWLO	FREE	WRERR	WREN	WR	RD
Access		R/W	R/W	R/S/HC	R/W/HS	R/W	R/S/HC	R/S/HC
Reset		0	0	0	x	0	0	0

Bit 6 – NVMREGS NVM Region Selection bit

Value	Description
`1`	Access EEPROM, DIA, DCI, Configuration, User ID and Device ID Registers
`0`	Access Program Flash Memory

Bit 5 – LWLO Load Write Latches Only bit

Value	Name	Description
`1`	When FREE = `0`	The next WR command updates the write latch for this word within the row; no memory operation is initiated
`0`	When FREE = `0`	The next WR command writes data or erases
-	Otherwise:	This bit is ignored

Bit 4 – FREE Program Flash Memory Erase Enable bit

Value	Description
`1`	Performs an erase operation with the next WR command; the 32-word pseudo-row containing the indicated address is erased (to all 1s) to prepare for writing
`0`	The next WR command writes without erasing

Bit 3 – WRERR

Write-Reset Error Flag bit^(1,2,3)

Reset States:

POR/BOR = x

All Other Resets = q

Value	Description
`1`	A write operation was interrupted by a Reset, interrupted Unlock sequence, or WR was written to one while NVMADR points to a write-protected address
`0`	All write operations have completed normally

Bit 2 – WREN Program/Erase Enable bit

Value	Description
`1`	Allows program/erase cycles
`0`	Inhibits programming/erasing of program Flash

Bit 1 – WR Write Control bit^(4,5,6)

Value	Name	Description
`1`	When NVMREG:NVMADR points to a Program Flash Memory location:	Initiates the operation indicated by table in the “WRERR Bit” section
`0`	When NVMREG:NVMADR points to a Program Flash Memory location:	NVM program/erase operation is complete and inactive
`1`	When NVMREG:NVMADR points to an EEPROM location:	Initiates an erase/program cycle at the corresponding EEPROM location
`0`	When NVMREG:NVMADR points to an EEPROM location:	NVM program/erase operation is complete and inactive

Bit 0 – RD Read Control bit⁽⁷⁾

Value	Description
`1`	Initiates a read at address = NVMADR1, and loads data to NVMDAT Read takes one instruction cycle and the bit is cleared when the operation is complete. The bit can only be set (not cleared) in software.
`0`	NVM read operation is complete and inactive

Bit is undefined while WR = 1 (during the EEPROM write operation it may be ‘0’ or ‘1’). Bit must be cleared by software; hardware will not clear this bit. Bit may be written to ‘1’ by the user to implement test sequences. This bit can only be set by following the sequence described in the “NVM Unlock Sequence” section. Operations are self-timed and the WR bit is cleared by hardware when complete. Once a write operation is initiated, setting this bit to zero will have no effect. Reading from EEPROM loads only NVMDATL.