37.2.7.2 Supported CCCs

When the Target receives a CCC from the Controller, the CCC code is stored in the I3CxCCC register. In addition, SCCCIF and UCCCIF interrupt flags are also set depending on whether the received CCC is supported or unsupported. The interrupt flags are set for all Broadcast CCCs and only for those Direct CCCs for which an address match occurs.

Important: The SADRIF and DADRIF address match flags are not set for CCC Transactions.

Tip: The user can use the CCC code stored in the I3CxCCC register in conjunction with UCCCIF interrupt flag to provide custom firmware support for unsupported CCCs.

Table 37-11. List of Supported Common Command Codes (CCC)
Common Command Code (CCC)	Type		Value	Brief Description
ENEC	Enable Events Command	Broadcast Write	`0x00`	Enable Target events such as Hot-Join and In-Band Interrupt (I3CxEC)
ENEC	Enable Events Command	Direct Write	`0x80`
DISEC	Disable Events Command	Broadcast Write	`0x01`	Disable Target events such as Hot-Join and In-Band Interrupt (I3CxEC)
DISEC	Disable Events Command	Direct Write	`0x81`
ENTDAA	Enter Dynamic Address Assignment	Broadcast Write	`0x07`	Enter Controller initiation of Dynamic Address Assignment Procedure
RSTDAA	Reset Dynamic Address Assignment	Broadcast Write	`0x06`	Discard current Dynamic Address and wait for new assignment
RSTDAA	Reset Dynamic Address Assignment	Direct Write⁽¹⁾	`0x86`	Discard current Dynamic Address and wait for new assignment
SETNEWDA	Set New Dynamic Address	Direct Write	`0x88`	Controller assigns new Dynamic Address to a Target
GETPID	Get Provisional ID	Direct Read	`0x8D`	Controller queries Target’s Provisional ID (I3CxPID0 through I3CxPID5)
GETDCR	Get Device Characteristics Register	Direct Read	`0x8F`	Controller queries Target’s Device Characteristics Register (I3CxDCR)
GETBCR	Get Bus Characteristics Register	Direct Read	`0x8E`	Controller queries Target’s Bus Characteristics Register (I3CxBCR)
GETSTATUS	Get Device Status	Direct Read	`0x90`	Controller queries Target’s operating status (I3CxDSTAT0 and I3CxDSTAT1)
RSTACT	Target Reset Action	Broadcast Write	`0x2A`	Controller configures and/or queries Target Reset action and timing (I3CxRSTACT)
RSTACT	Target Reset Action	Direct Write and Read	`0x9A`
SETMRL	Set Maximum Read Length	Broadcast Write	`0x0A`	Controller sets maximum read length (I3CxMRL) and IBI payload size (I3CxIBIPSZ)
SETMRL	Set Maximum Read Length	Direct Write	`0x8A`
SETMWL	Set Maximum Write Length	Broadcast Write	`0x09`	Controller sets maximum write length (I3CxMWL)
SETMWL	Set Maximum Write Length	Direct Write	`0x89`	Controller sets maximum write length (I3CxMWL)
GETMRL	Get Maximum Read Length	Direct Read	`0x8C`	Controller queries Target’s maximum possible read length (I3CxMRL) and IBI payload size (I3CxIBIPSZ)
GETMWL	Get Maximum Write Length	Direct Read	`0x8B`	Controller queries Target’s maximum possible write length (I3CxMWL)
GETMXDS	Get Maximum Data Speed	Direct Read	`0x94`	Controller queries Target’s maximum read and write data speeds (I3CxMRS, I3CxMWS) and maximum read turnaround time (I3CxMRT)
SETBUSCON	Set Bus Context	Broadcast Write	`0x0C`	Controller specifies a higher-level protocol and/or I3C specification version (I3CxBUSCXT)
Note: Direct RSTDAA CCC is not supported by MIPI I3C® Specification v1.1 onwards. Controllers adhering to MIPI I3C® Specification v1.0 are not recommended to use Direct RSTDAA CCC even though this Target module supports it.