37.4.10 I3CxERRIR0

Note:
  1. Will not self-clear after the event. The user must clear this bit to re-arm.
  2. This bit is valid in I2C mode only. For I3C mode, the process of Controller acknowledging bus arbitration request is handled separately through In-Band Interrupt and Hot-Join requests.
  3. This bit is set for all unsupported Broadcast CCCs and only for those unsupported Direct CCCs that address the Target.
  4. In case of a race condition, user writes always take precedence over hardware events.
Name: I3CxERRIR0
Address: 0x08C, 0x0BF

Error Interrupt Flag 0

Bit 76543210 
 I2CNACKIFTXUIFRXOIFHJEIFIBIEIFBUSEIFBTOIFUCCCIF 
Access R/W/HS R/W/HS R/W/HS R/W/HS R/W/HS R/W/HS R/W/HS R/W/HS  
Reset 00000000 

Bit 7 – I2CNACKIF  I2C Not-Acknowledge (NACK) Received(1, 2)

ValueDescription
1 NACK received from Controller during I2C Transmit
0 NACK not received during I2C Transmit

Bit 6 – TXUIF  Transmit Underrun(1)

ValueDescription
1 An underrun occurred during Private/I2C Read request
0 Transmit underrun not occurred

Bit 5 – RXOIF  Receive Overrun(1)

ValueDescription
1 An overrun occurred during Private/I2C Write transaction
0 Receive overrun not occurred

Bit 4 – HJEIF  Hot-Join Error Interrupt Flag(1)

ValueDescription
1 The Hot-Join retry limit (I3CxRETRY) exceeded or Bus Timeout occurred immediately after Hot-Join request was made
0 The Hot-Join retry limit (I3CxRETRY) not exceeded

Bit 3 – IBIEIF  In-Band Interrupt Error Flag(1)

ValueDescription
1 The In-Band Interrupt retry limit (I3CxRETRY) exceeded or Bus Timeout occurred immediately after IBI request was made
0 The In-Band Interrupt retry limit (I3CxRETRY) not exceeded

Bit 2 – BUSEIF  Bus Error (TE0-TE6 Error) Interrupt Flag(1)

ValueDescription
1 TE0-TE6 Error (I3CxBSTAT) occurred
0 TE0-TE6 Error (I3CxBSTAT) not occurred

Bit 1 – BTOIF  Bus Time-out(1)

ValueDescription
1 Bus Time-out (I3CxBTO) occurred
0 Bus Time-out (I3CxBTO) not occurred

Bit 0 – UCCCIF  Unsupported CCC Received(1, 3)

ValueDescription
1 An unsupported CCC was received
0 No unsupported CCC was received
Will not self-clear after the event. The user must clear this bit to re-arm. This bit is valid in I2C mode only. For I3C mode, the process of Controller acknowledging bus arbitration request is handled separately through In-Band Interrupt and Hot-Join requests. This bit is set for all unsupported Broadcast CCCs and only for those unsupported Direct CCCs that address the Target. In case of a race condition, user writes always take precedence over hardware events.