37.4.36 I3CxDSTAT0

Note:
  1. This Target module does not support Activity Status, hence the meaning of these bits is up to the vendor to define and is to be communicated to the Controller through a private agreement.
  2. This bit is set alongside BUSEIF bit when a bus error is detected.
  3. This byte is the lower byte read by the Controller during a GETSTATUS CCC.
  4. To ensure expected behavior, this register should only be written when the module is disabled (EN = 0).
Name: I3CxDSTAT0
Address: 0x0AA, 0x0DD

Device Status 0

Bit 76543210 
 ACTMODE[1:0]PERRINTPEND[3:0] 
Access R/WR/WR/HS/HCR/WR/WR/WR/W 
Reset 0000000 

Bits 7:6 – ACTMODE[1:0]  Activity Mode(1)

The Target’s activity state for monitoring by the Controller.

Bit 5 – PERR  Protocol Error(2)

ValueDescription
1 The Target detected a protocol error since the last Status read (the bit self-clears after the Controller successfully reads the Target’s status)
0 The Target has not detected a protocol error since the last Status read

Bits 3:0 – INTPEND[3:0]  Pending Interrupt

ValueDescription
other The interrupt number of the highest priority pending interrupt
0 There is no pending interrupt
This Target module does not support Activity Status, hence the meaning of these bits is up to the vendor to define and is to be communicated to the Controller through a private agreement. This bit is set alongside BUSEIF Bus Error (TE0-TE6 Error) Interrupt Flag(1) bit when a bus error is detected. This byte is the lower byte read by the Controller during a GETSTATUS CCC. To ensure expected behavior, this register should only be written when the module is disabled (EN Target Enable = 0).