3.2.4 Mi-V Processor Subsystem

The Mi-V processor subsystem configures Core10GMAC and CoreUSXGMII through Advanced High-performance Bus-Advanced Peripheral Bus (AHB-APB) interface. It also communicates with external AQR107 PHY through CoreGPIO which provides the MDIO clause 45 interface implemented in the firmware.

MIV_RV32IMA_L1_AHB Configurator sets the Reset Vector Address to 0x80000000, as shown in the preceding figure. This is the address which the processor starts executing after a reset. The processor's main memory must be accessible to Mi-V AHB memory interface whose memory-mapped address ranges from 0x80000000 to 0x8FFFFFFF. The Mi-V memory interface supports cached transactions, whereas Mi-V MMIO interface does not support them.

Mi-V subsystem communicates to the IP block using the following interfaces:

• Core10GMAC: Mi-V (AHB initiator) > CoreAHBlite (AHB initiator) > CoreAHB_to_APB3 (APB initiator) > Core10GMAC (APB target). The following table lists the registers configured by Mi-V subsystem.

  Table 3-2. Core10GMAC Registers

  Register Address		Offset	Bit	Binary value
  MAC TX Config Register (0xA)		0x3	cfg_sys_mac_tx_en	1
  		0x4	sys_mac_tx_fcs_ins	1
  MAC RX Config Register (0xB)		0x0	mac_rx_fcs_remove	1
  		0x3	cfg_sys_mac_rx-en	1

• CoreUSXGMII: Mi-V (AHB initiator) > CoreAHBlite (AHB initiator) > CoreAHB_to_APB3 (APB initiator) > CoreUSXGMII (APB target). Registers configured by Mi-V subsystem are listed in the following table.

  Table 3-3. CoreUSXGMII Registers

  Register	Offset	Description
  USXGMII-CONTROL_REG	0x0	Control: Enables/Disables the USXGMII Auto negotiation function
  USXGMII_STATUS_REG	0x4	Status: Indicates the link status along with auto negotiation status
  USXGMII_AN_ADV	0x8	Auto Negotiation Advertise: Configures the mode of operation and configures the speed selection
  USXGMII_AN_LP_ADV	0xC	Auto Negotiation Link Partner Base Page Ability: Read Only register indicates the link partners USXGMII configuration

• CoreUARTAPB: Mi-V (AHB initiator) > CoreAHBlite (AHB initiator) > CoreAHB_to_APB3 (APB initiator) > CoreUARTAPB (APB target).
• Aquantia PHY (AQR107): Mi-V (AHB initiator) > CoreAHBlite (AHB initiator) > CoreAHB_to_APB3 (APB initiator) > CoreGPIO (APB target). The following table lists the registers configured by Mi-V subsystem.

  Table 3-4. PHY Registers

  Register	Offset	Description
  PHY REGISTER	0x4	Enables/Disables/re-start Auto Negotiation Note: For information about the features and registers of Aquantia PHY, see AQR107 Handbook.

• PF_SRAM: The PolarFire system controller initializes the LSRAMs with user application and releases the system reset.