3.2.1 Core10GMAC

The Core10GMAC IP is the 10 Gbps Ethernet MAC that transmits and receives the Ethernet packets.

Core10GMAC is configured for XGMII mode with a core data width of 64 bits. Core data width is the width of the data path connected to the USXGMII IP. The system data width, that is, the width of the interface to the user logic, is configured as 64 bits. In this demo, the FiFo_wrapper_Top module provides this interface. The TX and RX Pause features are disabled, and both the MAC TX FIFO depth and MAC RX FIFO depth are set to 256.

The Core10GMAC IP is configured using Mi-V soft processor and is covered in-detail in the Mi-V subsystem section. For information about the features and registers of Core10GMAC, see Core10GMAC User Guide.