3.2.8 PF_CCC

The PF_CCC IP instances provide the required clock frequency for CoreUSXGMII, Core10GMAC, and FIFO logic. The PolarFire Clock Conditioning Circuitry (CCC) block sources an input clock of 148.5 MHz from the FAB_REF_CLK signal (output of PF_XCVR_REF_CLK) and generates a 50 MHz clock at OUT0 and 156.25 at OUT1. The OUT0 port of CCC is used for the configuration and OUT1 is used for the user logic in the design.

Mi-V soft processor receives speed information from configuring the PF_CCC instantiations through the DRI interface, see the following figure.

Figure 3-3. Mi-V Soft Processor - DRI - PF_CCC Interface

The following table lists the clocks generated by PF_CCC instantiations used for generating RX and TX clocks for USXGMII and Core10GMAC.

Table 3-5. USXGMII and Core10GMAC Clock Sources
PF_CCC InstanceInput SourceOutput Clocks
CCC_XCVR_Rx_Ref_0XCVR_RX_CLKUSXGMII_core_rx_clk
Core10GMAC_Icore_rx_clk
PF_CCC_0PF_XCVR_REF_CLK_1USXGMII_core_tx_clk
Core10GMAC_Icore_tx_clk

For more information, see Clocking Structure.