24.5.1 Behavioral Simulation

Use the following procedure to perform a behavioral simulation of a design using the ModelSim simulator. Type UNIX commands at the UNIX prompt. Type PC commands on the command line of the ModelSim Transcript window. The commands below are for PC. To make the commands work for UNIX, use forward slashes instead of back slashes.

1. Invoke the simulator (PC only).
2. Change the directory to your project directory. This directory must include your Verilog design files and testbench. Type the following command:

   cd <project_dir>

3. Create a “work” directory. Type the following command:

   vlib work

   vmap work ./work

4. Compile your design source and testbench file(s). Before simulating your design, you must compile the source files and testbench. For hierarchical designs, compile the lower-level design blocks before the higher-level design blocks. Type the following commands:

   vlog <behavioral_design_file>.v

   vlog <test_bench>.v

5. Simulate your design. Type the following command:

   vsim <topmost_module_name>

   For example:

   vsim test_adder_behave

   The module test_adder_behave in the testbench will be simulated.

   If any Microchip cores are instantiated in your Verilog source, use the following command to simulate your design with the compiled Microchip Verilog library.

   vsim -L $ALSDIR\lib\vlog\mti\<act_fam> <topmost_module_name>