24.5.3 Timing Simulation

Use the following procedure to perform a timing simulation of a design using the ModelSim simulator. Type UNIX commands at the UNIX prompt. Type PC commands on the command line of the ModelSim Transcript window. The commands below are for PC. To make the commands work for UNIX, use forward slashes instead of back slashes.

  1. Place-and-route your design in Designer. Refer to the Designer User’s Guide for information about placing-and-routing a design using Designer.
  2. Extract timing information for your design from Designer. Choose the Export command from the File menu or click Back Annotate. The Extract dialog is displayed. Create a

    <design_name>.sdf file by choosing the SDF option from the CAE pull-down menu. Click OK.

  3. Invoke the simulator (PC only).
  4. Change the directory to your project directory. This directory must include your Verilog design files and testbench. Type the following command:

    cd <project_dir>

  5. Create a “work” directory. You only need to create a work directory if you are using a different project directory than the one you used for behavioral and structural simulation. Type the following command:

    vlib work

  6. Compile the structural netlist and testbench. If you have not already generated a structural Verilog netlist, go to “Generating a Structural Verilog Netlist” for the procedure. Type the following commands:

    vlog <structural_netlist>.v

    vlog <test_bench>.v

  7. Simulate your design using timing information contained in the SDF file. Type the following command:
    vsim -L $ALSDIR\lib\vlog\mti\<act_fam> -sdf[max|typ|min]
/<region>=<design name>.sdf -c <topmost_module_name>

    The <region> option specifies the region (or path) to an instance in a design where back annotation begins. You can use it to specify a particular FPGA instance in a larger system design or testbench that you wish to back annotate. For example:

    vsim -L $ALSDIR\lib\vlog\mti\42mx -sdfmax /uut=adder.sdf -c
test_adder_structural

In this example, the module “adder” has been instantiated as instance “uut” in the testbench. The module named “test_adder_structural” in the testbench will be simulated using the maximum delays specified in the SDF file.