24.5.2 Structural Simulation

Use the following procedure to perform a structural simulation of a design using the ModelSim simulator. Type UNIX commands at the UNIX prompt. Type PC commands on the command line of the ModelSim Transcript window. The commands below are for PC. To make the commands work for UNIX, use forward slashes instead of back slashes.

1. Invoke the simulator (PC only).
2. Change directory to your project directory. This directory must include your Verilog design files and testbench. Type the following command:

   cd <project_dir>

3. Create a “work” directory. You only need to create a work directory if you are using a different project directory than the one you used for behavioral simulation. Type the following command:

   vlib work

4. Compile the structural netlist and testbench. If you have not already generated a structural Verilog netlist, go to “Generating a Structural Verilog Netlist” for the procedure. Type the following commands:

   vlog <structural_netlist>.v vlog <test_bench>.v

5. Simulate your design. Type the following commands:

   vsim -L $ALSDIR\lib\vlog\mti\<act_fam> <topmost_module_name>

   For example:

   vsim -L $ALSDIR\lib\vlog\mti\42mx test_adder_structure

   The module test_adder_structure in the testbench will be simulated using the compiled 42MX Verilog library.