13.10.2 Floorplanning a Designer Block

Microchip recommends that you floorplan your Designer Block component (in MVN or with PDC commands) to ensure that your Designer Block is placed in a specific region. If you do not restrict your Designer Block placement, it may be placed anywhere on your die; see the define_region PDC command.

It is also important to consider the placement of all interface macros in the boundaries of these regions. This facilitates the interconnection of the Designer Block to the top-level design. If the Designer Block is highly optimized (densely packed) there may be no routing channels available to connect to any internal Designer Block interface macro. Placing all interfaces at Designer Block boundaries helps you eliminate routability issues, routing congestion, and failure.

Designer-Block specific features in MVN are:

• Block Ports tab - Lists all the ports in a Designer Block even if they are not connected to I/Os.
• Interface Instances in Designer Block creation (in the Active Lists) - Lists all macros connected to ports. These macros must be placed on the boundary of your Designer Block region, since they will be connected to the <top> design.
• Designer Block content available when you instantiate a Designer Block in the <top> design (in Active Lists) - Lists all macros in the Designer Block.
• A block tab that lists all the blocks in your design.
• Search support that enables you to find a specific block in your design.
• Show the routing of locked nets from the Designer Blocks immediately after compile is complete; no need to wait until layout is finished since the routing is locked and will not be changed.