8.7.2 Timing Simulation

ViewSim timing simulation is no longer supported by Actel since the Innoveda back-annotate feature is not available in the Actel Designer software any more. To perform timing simulation:

1. Export a VHDL or Verilog nelist and *.sdf file from the Actel Designer software
2. Use the HDL netlist and *.sdf file to run timing simulation in other HDL based simulators