11.3.5 Register Duplication

The delay on a net rises as the number of loads increase in the antifuse architecture. This is acceptable for networks such as reset, but not others such as tri-state enable, etc. It is important to keep the fanout of a network below 16. In the following VHDL example, the signal “Tri_en” has a fanout of 24.

Figure 11-30. Register Duplication Example

architecture load of four_load is
signal Tri_en std_logic;
begin
loadpro: process (Clk)
begin
if (clk'event and clk ='1') then
Tri_end <= Tri_en;
end if;
end process loadpro;
endpro : process (Tri_end, Data_in)
begin
if (Tri_end = '1') then
out <= Data_in;
else
out <= (others => 'Z');
end if;
end process endpro;
end load;

To decrease the fanout by half, registers are duplicated on the signal “Tri_en” so the load is split in half, as shown in the following example.

Note: Some synthesis tools duplicate registers to resolve timing and fanout violations and do not require this coding technique.

Figure 11-31. Duplicated Registers with a Load Split in Half to Decrease Fanout

architecture loada of two_load is
signal Tri_en1, Tri_en2 : std_logic;
begin
loadpro: process (Clk)
begin
if (clk'event and clk ='1') then
Tri_en1 <= Tri_en;
Tri_en2 <= Tri_en;
end if;
end process loadpro;
process (Tri_en1, Data_in)
begin
if (Tri_en1 = '1') then
out(23:12) <= Data_in(23:12);
else
out(23:12) <= (others => 'Z');
end if;
end process;
process (Tri_en2, Data_in)
begin
if (Tri_en2 = '1') then
out(11:0) <= Data_in(11:0);
else
out(11:0) <= (others => 'Z');
end if;
end process;