11.3.3 Operators Inside Loops

Operators are resource intensive compared to multiplexors. If there is an operator inside a loop, the synthesis tool has toevaluate all conditions. In the following VHDL example, the synthesis tool builds four adders and one multiplexor. This implementation is only advisable if the select line “req” is a late arriving signal.

Figure 11-26. Four Adders and One Multiplexor Example

vsum := sum;
for i in 0 to 3 loop
if (req(i)='1') then
vsum <= vsum + offset(i);
end if;
end loop;

If the select line “req” is not critical, the operator should be moved outside the loop so the synthesis tool can multiplex the data before performing the adder operation. The area efficient design is implemented in a larger multiplexor and a single adder, as shown below.

Figure 11-27. Larger Multiplexor and Single Adder Example

vsum := sum;
for i in 0 to 3 loop
if (req(i)='1') then
offset_1 <= offset(i);
end if;
end loop;
vsum <= vsum + offset_1;