11.3.4 Coding for Combinability

Combinatorial modules in ACT2, ACT3, DX, and MX families can be merged into sequential modules in the antifuse architecture. This results in a significant reduction in delay on the critical path as well as area reduction. However, cells are only merged if the combinatorial module driving a basic flip-flop has a load of 1. In the following VHDL example, the AND gate driving the flip-flop has a load of 2. As a result, the AND gate cannot be merged into the sequential module.

Figure 11-28. Coding for Compatibility Example
one :process (clk, a, b, c, en) begin
if (clk'event and clk ='1') then
if (en = '1') then
q2 <= a and b and c;
end if;
q1 <= a and b and c;
end if;
end process one;

To enable merging, the AND gate has to be duplicated so that it has a load of 1. To duplicate the AND gate, create two independent processes, as shown below. Once merged, one logic level has been removed from the critical path.

Note: Some synthesis tools automatically duplicate logic on the critical path. Other synthesis tools detect the function “a & b & c” in the two processes and share the function on a single gate. If the function is shared, the logic is not duplicated and you should consider instantiation.
Figure 11-29. Two Independent Processes
part_one: process (clk, a, b, c, en) begin
if (clk'event and clk ='1') then
if (en = '1') then
q2 <= a and b and c;
end if;
end if;
end process part_one;
part_two: process (clk, a, b, c) begin
if (clk'event and clk ='1') then
q1 <= a and b and c;
end if;
end process part_two;