7.4.10 Generating a Structural VHDL Netlist

You can generate a structural VHDL netlist from your EDIF netlist by either exporting it from Designer or by using the “edn2vhdl” program. The structural VHDL netlist generated by Designer and the “edn2vhdl” use std_logic for all ports. The bus ports are in the same bit order as they appear in the EDIF netlist.

To generate a structural VHDL netlist using Designer,

1. Invoke Designer.
2. Import your EDIF netlist. Select the Import Netlist command from the File menu. The Import Netlist dialog box is displayed. Specify EDIF as the Netlist Type, GENERIC (or Innoveda if you are using a Innoveda synthesis tool) as the Edif Flavor, and VHDL as the Naming Style. Type the full path name of your EDIF netlist or use the Browse button to select your design. Click OK.
3. Export a structural VHDL netlist. Select the Export command from the File menu. The Export dialog box is displayed. Specify Netlist File as the File Type and VHDL as the Format. Click OK.

To generate a structural VHDL netlist using edn2vhdl,

1. Change to the directory that contains the EDIF netlist.
2. Type the following command at the prompt:

   edn2vhdl fam:<act_fam> <design_name>