11.4.7 SmartGen Counter

Several synthesis tools cannot build an optimal counter implementation for the Microchip architecture. If a counter is on a critical path, this implementation can increase logic level usage and decrease performance. To reduce critical path delays and to achieve optimal results from your design, Microchip recommends that you instantiate counters generated by the SmartGen Core Builder. The SmartGen Core Builder supports a wide variety of counters for area and performance needs.

Figure below uses a 5-bit counter with load, count enable, and asynchronous reset that has been generated with SmartGenand saved as a structural HDL netlist called “CNT5”. The counter is instantiated as follows:

Figure 11-41. Instantiating a 5-Bit Counter

VHDL

library IEEE;
use IEEE.std_logic_1164.all;
entity counter is
port (bus_d : in std_logic_vector(4 downto 0);
bus_q : out std_logic_vector(4 downto 0);
net_clock, net_aclr, net_enable : in std_logic;
net_sload : in std_logic);
end counter;
architecture rtl of counter is
-- Component Declaration
component CNT5
port (Data : in std_logic_vector(4 downto 0);
Sload, Enable, Aclr, Clock : in std_logic;
Q : out std_logic_vector(4 downto 0));
end component;
begin
-- Concurrent Statement
U0 : CNT5 port map (Data => bus_d,
Sload => net_sload,
Enable => net_enable,
Aclr => net_aclr,
Clock => net_clock,
Q => bus_q);
end rtl;

Verilog

module counter (bus_q, bus_d, net_clock, net_aclr, net_enable,
net_sload);
input [4:0] data;
input net_sload, net_enable, net_aclr, net_clock;
output [4:0] bus_q;
CNT5 U0 (.Q(bus_q), .Data(bus_d), .Clock(net_clock), .Aclr(net_aclr),
.Enable(net_enable), .Sload(net_sload));
endmodule