11.4.4 Registered I/Os

This is the start of your topic. The ACT3 technology has registers in the I/O ring, with both reset and preset, which allow for fast input setup and clock-to-out delays. Because most synthesis tools do not infer these special resources, the following example shows how to instantiate a registered I/O cell, BREPTH, in your design.

VHDL

library IEEE;
use IEEE.std_logic_1164.all;
entity regio is
port (data, en, Tri_en, clock, preset : in std_logic;
bidir : inout std_logic;
q_pad : out std_logic);
end regio;
architecture rtl of regio is
-- Component Declaration
component BREPTH
port (D, ODE, E, IOPCL, CLK : in std_logic;
Y : out std_logic;
PAD : inout std_logic);
end component;
begin
-- Concurrent Statement
U0 : BREPTH port map ( D => data,
ODE => en,
E => Tri_en,
IOPCL => preset,
CLK => clock,
Y => q_pad,
PAD => bidir);
end rtl;

Verilog

module regio (data, Q_pad, clock, preset, Tri_en, en, bidir);
input data, clock, preset, Tri_en, en;
output Q_pad;
inout bidir;
BREPTH U1 (.PAD(Q_pad), .D(data), .CLK(clock), .IOPCL(preset), .E(Tri_en), .ODE(en),
.Y(bidir));
endmodule

Note: As a good design practice, instantiate all input/output cells at the top level of your design.