3.6.1.2.1 Data FIFO Configuration Register


Bit	7	6	5	4	3	2	1	0
	DFDRA		DFFLC[5:0]
Access	R/W	R	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 7 – DFDRA Data FIFO Direct Read Access Operational Mode

This bit defines the operational mode of the data FIFO.


DFDRA	Description
`0`	Direct write access: The FIFO is configured for data reception. The AVR^® can only read from the FIFO. Write access is allowed via the direct write access interface from the RX buffer.
`1`	Direct read access: The FIFO is configured for data transmission. The AVR can only write to the FIFO. Read access is allowed via the direct read access interface from the TX modulator.

Bit 6 – Reserved Bit

This bit is reserved and always returns ‘0’ when read.

Bits 5:0 – DFFLC[5:0] Data FIFO Fill Level Configuration

The DFFLC bits define the required fill level for setting the DFS.DFFLRF status flag and triggering an interrupt. Precise conditions for this event are described at the DFS.DFFLRF bit. Valid DFFLC values are 0..32. Values exceeding this do not set the status flag or trigger an interrupt.

Name:	DFC
Offset:	0x0DA
Reset:	0x00