Writing a ‘1’
to this bit location clears the data FIFO. RdPtr, WrPtr and fill level are reset to
‘0’. The data FIFO status (DFS) and telegram length
(DFTLH/DFTLL) registers are cleared. The data FIFO configuration registers (DFC and
DFI) keep their settings. The data content of the FIFO is also retained. It can be
recovered by RdPtr and WrPtr manipulations. Reading this bit always returns
‘0’.
Bit 6 – Reserved
Bit
This bit is reserved and
always returns ‘0’ when read.
Bits 5:0 – DFFLS[5:0] Data FIFO Fill
Level Status
The current fill level of the
data FIFO is stored in DFFLS. These bits are read-only. A DFFLS value that is larger
than 32 indicates incorrect programming of the read (DFRP) or write (DFWP) pointer.
The fill level is updated one system clock cycle after a read/write access or
pointer manipulation.
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
