3.6.1.2.9 DFS – Data FIFO
Status Register
| Name: | DFS |
| Offset: | 0x0D2 |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | | | | DFOFL | DFUFL | DFFLRF | |
| Access | R | R | R | R | R | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – Reserved
Bit
This bit is reserved and
always returns ‘0’ when read.
Bit 6 – Reserved
Bit
This bit is reserved and
always returns ‘0’ when read.
Bit 5 – Reserved Bit
This bit is reserved and
always returns ‘0’ when read.
Bit 4 – Reserved Bit
This bit is reserved and
always returns ‘0’ when read.
Bit 3 – Reserved Bit
This bit is reserved and
always returns ‘0’ when read.
Bit 2 – DFOFL Data FIFO Overflow
Flag
This error flag bit is set if
there is write access to a full FIFO or if the fill level is higher than the FIFO
depth, which can happen due to faulty pointer manipulations in the DFRP or DFWP
registers. The DFOFL flag can generate an interrupt when masked in DFI.DFERIM. The
DFOFL flag is automatically cleared when the interrupt is executed or by writing a
‘1’ to its bit location.
Bit 1 – DFUFL Data FIFO Underflow Flag
This error flag bit is set if
there is a read access to an empty FIFO. The DFUFL flag can generate an interrupt
when masked in DFI.DFERIM. The DFUFL flag is automatically cleared when the
interrupt is executed or by writing a ‘1’ to its bit
location.
Bit 0 – DFFLRF Data FIFO Fill Level Reached Status
Flag
- If DFC.DFDRA =
0, this flag is set if the current fill level of the
data FIFO matches the fill level configuration (DFC.DFFLC) after the
reception of a byte.
- If DFC.DFDRA =
1, this flag is set if the current fill level of the
data FIFO matches the fill level configuration (DFC.DFFLC) after the
transmission of a byte.
- The DFFLRF flag generates an
interrupt when masked in DFI.DFFLIM. The DFFLRF flag is automatically
cleared when the interrupt is executed or by writing a ‘
1’
to its bit location.
