3.10.2.4 General Purpose Register File

The register file is optimized for the AVR Enhanced RISC instruction set. To achieve the required performance and flexibility, the following input/output schemes are supported by the register file:

One 8-bit output operand and one 8-bit result input two 8-bit output operands and one 8-bit result input two 8-bit output operands and one 16-bit result input One 16-bit output operand and one 16-bit result input.

The following figure shows the structure of the 32 general purpose working registers in the CPU.

Most of the instructions operating on the register file have direct access to all registers, and most of them are single cycle instructions.

As shown in preceding table, each register is also assigned to a data memory address, mapping them directly into the first 32 locations of the user data space. Although not physically implemented as SRAM locations, this memory organization provides considerable flexibility in accessing the registers because the X, Y and Z pointer registers can be set to index any register in the file.