3.9.4 PLL Lock State Machine

The PLL lock state machine activates the PLL speed-up mode for faster locking; then, waits for the PLL lock signal. The necessary sequence to read the lock flag is passed a maximum of three times. If no lock is reached by that point, the state machine ends with the error flag set.

Depending on the settings gathered in Table 3-54, this state machine enables the ADC and the IF amplifier.

After having successfully passed the PLL lock state machine, the RF frequency must be up and running and the design can be put into RxMode or TxMode by starting either the RX DSP enable or the TX DSP enable state machine.