3.9.16 Interaction with IO Registers

The following table shows all the IO registers that are read or modified by the sequencer state machine. While the state machine is running, it is forbidden to write to any of these registers. Failure to observe this may cause unpredictable or faulty behavior of the state machine.

Reading is always allowed, but in the case of RF front-end registers, doing so can lead to timing deviations (delay the register access of the state machine).

The table also marks the different types of access performed by the corresponding sub-state machine. Set means the bit is set to ‘1’. Clear means the bit is set to ‘0’. Set & clear means both settings are done throughout the sub-state machine sequence; for example, set at the beginning and cleared later on or at the end. Value means this register is accessed as a whole, writing a value into it. No single bit operations are done on these registers. Read means the state machine is only reading the indicated bit.

The following figure shows the control register access from the state machines.
Figure 3-45. Control Register Access from State Machines

Note:
  • Legend
    • Clear: This bit can be cleared by the state machine.
    • Set: This bit can be set to ‘1’ by the state machine.
    • Set&clear: This bit can be set to ‘1’ and/or cleared by the state machine. The value can depend on measurements, e.g., as for the FECR.ANDP, or it can be enabled at the beginning and cleared at the end of an operation, e.g., as for the FEEN1.ATEN.
    • Value: A multi-bit value is written to this register.
    • Read: This value gets read by the state machine.