3.10.8.2 Data Modes

There are four combinations of SCK phase and polarity with respect to serial data, which are determined by the control bits CPHA and CPOL. The SPI data transfer formats are shown in the following figure. Data bits are shifted out and latched in on opposite edges of the SCK signal, ensuring sufficient time for data signals to stabilize. This functionality is shown in detail in the following table.

Table 3-104. CPOL and CPHA Functionality

Leading Edge

Trailing Edge

SPI Mode

CPOL = 0, CPHA = 0

Sample (rising)

Setup (falling)

0 (default mode for the ATA8510/15)

CPOL = 0, CPHA = 1

Setup (rising)

Sample (falling)

1

CPOL = 1, CPHA = 0

Sample (falling)

Setup (rising)

2

CPOL = 1, CPHA = 1

Setup (falling)

Sample (rising)

3

Figure 3-90. SPI Transfer Format with CPHA = 0

The SPI interface can operate in Client mode as shown in the preceding figure.

The SPI data transfer formats are shown in the following figure.

Figure 3-91. SPI Transfer Format with CPHA = 1

The SPI interface can operate in Client mode as shown in the preceding figure.

The reset values after the first power-on are:

CPOL = 0 Clock polarity CPHA = 0 Clock phase

DORD = 0 Data order

CPOL, CPHA and DORD are stored in the EEPROM and can be changed in the configuration tool if required for a specific application.