1 Device Overview

This document contains device-specific information for the dsPIC33CDVL256MC506 Digital Signal Controller (DSC) devices.

dsPIC33CDVL256MC506 devices contain extensive Digital Signal Processor (DSP) functionality with a high-performance, 16-bit MCU architecture.

Figure 1-1. dsPIC33CDVL256MC506

Note:

Device Interconnections are shown in Table 1-1.

Only applies to devices with the LIN transceiver module. Please see dsPIC33CDVL256MC506 Product Families for more information

Table 1-1. dsPIC33CDVL256MC506 Family Interconnections
Host Connection	Module Connection	Pin
dsPIC^® DSC Connection	MOSFET Gate Driver Connection	External Pin
RB14/PWM1H	PWMAH	10
RB15/PWM1L	PWMAL	No
RB12/PWM2H	PWMBH	54
RB13/PWM2L	PWMBL	No
RB10/PWM3H	PWMCH	53
RB11/PWM3L	PWMCL	No
RD1	FAULT	No
RC12/RP60	DE2	No
RC13	OE	No
dsPIC DSC Connection	LIN Transceiver Connection⁽²⁾	External Pin
RC10	LIN_EN	No
RC5/RP53	LIN_TXD	No
RC11/RP59	LIN_RXD	No
Note: Interconnect is also bonded to an external device pin. Only applies to devices with LIN Transceiver module.

Figure 1-2 shows a general block diagram of the core and peripheral modules of the dsPIC33CDVL256MC506 family.

Figure 1-2. dsPIC33CDVL256MC506 Family Block Diagram⁽¹⁾

Note:

The numbers in the parentheses are the number of instantiations of the module indicated.
Not all I/O pins or features are implemented on all device pinout configurations. See Table 1-2 for specific implementations by pin count.
Some peripheral I/Os are only accessible through Peripheral Pin Select (PPS).

Table 1-2. Pinout I/O Descriptions
Pin Name⁽¹⁾	Pin Type	Buffer Type	PPS	Description
AN0-AN19 ANN0	I I	Analog Analog	No No	Analog input channels Analog negative input
ADCTRG	I	ST	Yes	ADC Trigger Input 31
CAN1RX CAN1TX	I O	ST —	Yes Yes	CAN1 receive input CAN1 transmit output
CLKI CLKO	I O	ST/CMOS —	No No	External Clock (EC) source input. Always associated with OSCI pin  function. Oscillator crystal output. Connects to the crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSCO pin function.
OSCI OSCO	I I/O	ST/CMOS —	No No	Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. Oscillator crystal output. Connects to the crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes.
REFCLKI	I	ST	Yes	Reference clock input
REFCLKO	O	—	Yes	Reference clock output
INT0 INT1 INT2 INT3	I I I I	ST ST ST ST	No Yes Yes Yes	External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3
IOCA[4:0] IOCB[15:0] IOCC[15:0] IOCD[15:0]	I I I I	ST ST ST ST	No No No No	Interrupt-on-Change input for PORTA Interrupt-on-Change input for PORTB Interrupt-on-Change input for PORTC Interrupt-on-Change input for PORTD
QEIA1 QEIB1 QEINDX1 QEIHOM1 QEICMP	I I I I O	ST ST ST ST —	Yes Yes Yes Yes Yes	QEI Input A QEI Input B QEI Index 1 input QEI Home 1 input QEI comparator output
RA0-RA4	I/O	ST	No	PORTA is a bidirectional I/O port
RB0-RB15	I/O	ST	No	PORTB is a bidirectional I/O port
RC0-RC15	I/O	ST	No	PORTC is a bidirectional I/O port
RD0-RD15	I/O	ST	No	PORTD is a bidirectional I/O port
T1CK	I	ST	Yes	Timer1 external clock input
U1CTS U1RTS U1RX U1TX U1DSR U1DTR	I O I O I O	ST — ST — ST —	Yes Yes Yes Yes Yes Yes	UART1 Clear-to-Send UART1 Request-to-Send UART1 receive UART1 transmit UART1 Data-Set-Ready UART1 Data-Terminal-Ready
U2CTS U2RTS U2RX U2TX U2DSR U2DTR	I O I O I O	ST — ST — ST —	Yes Yes Yes Yes Yes Yes	UART2 Clear-to-Send UART2 Request-to-Send UART2 receive UART2 transmit UART2 Data-Set-Ready UART2 Data-Terminal-Ready
U3CTS U3RTS U3RX U3TX U3DSR U3DTR	I O I O I O	ST — ST — ST —	Yes Yes Yes Yes Yes Yes	UART3 Clear-to-Send UART3 Request-to-Send UART3 receive UART3 transmit UART3 Data-Set-Ready UART3 Data-Terminal-Ready
SENT1 SENT1OUT	I O	ST —	Yes Yes	SENT1 input SENT1 output
PTGTRG24 PTGTRG25	O O	— —	Yes Yes	PTG Trigger Output 24 PTG Trigger Output 25
TCKI1-TCKI4 ICM1-ICM4 OCFA-OCFB OCM1-OCM4	I I I O	ST ST ST —	Yes Yes Yes Yes	SCCP Timer Inputs 1 through 4 SCCP Capture Inputs 1 through 4 SCCP Fault Inputs A through B SCCP Compare Outputs 1 through 4
SCK1 SDI1 SDO1 SS1	I/O I O I/O	ST ST — ST	Yes Yes Yes Yes	Synchronous serial clock input/output for SPI1 SPI1 data in SPI1 data out SPI1 Slave synchronization or frame pulse I/O
SCK2 SDI2 SDO2 SS2	I/O I O I/O	ST ST — ST	Yes Yes Yes Yes	Synchronous serial clock input/output for SPI2 SPI2 data in SPI2 data out SPI2 Slave synchronization or frame pulse I/O
SCL1 SDA1 ASCL1 ASDA1	I/O I/O I/O I/O	ST ST ST ST	No No No No	Synchronous serial clock I/O for I2C1 Synchronous serial data I/O for I2C1 Alternate synchronous serial clock I/O for I2C1 Alternate synchronous serial data I/O for I2C1
TMS TCK TDI TDO	I I I O	ST ST ST —	No No No No	JTAG Test mode select pin JTAG test clock input pin JTAG test data input pin JTAG test data output pin
PCI8-PCI22 PWMEA-PWMED PWM1L-PWM4L⁽²⁾ PWM1H-PWM4H⁽²⁾	I O O O	ST — — —	Yes Yes No No	PWM Inputs 8 through 22 PWM Event Outputs A through D PWM Low Outputs 1 through 4 PWM High Outputs 1 through 4
CLCINA-CLCIND CLC1OUT-CLC4OUT	I O	ST —	Yes Yes	CLC Inputs A through D CLC Outputs 1 through 4
CMP1 CMP1A CMP1B CMP1C CMP1D	O I I I I	— Analog Analog Analog Analog	Yes No No No No	Comparator 1 output Comparator Channel 1A input Comparator Channel 1B input Comparator Channel 1C input Comparator Channels 1D input
CMP2 CMP2A CMP2B CMP2C CMP2D	O I I I I	— Analog Analog Analog Analog	Yes No No No No	Comparator 2 output Comparator Channel 2A input Comparator Channel 2B input Comparator Channel 2C input Comparator Channels 2D input
DACOUT1	O	—	No	DAC output voltage
IBIAS0-IBIAS3 ISRC0-ISRC3	O O	Analog Analog	No No	50 μA Constant-Current Outputs 0 through 3 10 μA Constant-Current Outputs 0 through 3
OA1IN+ OA1IN- OA1OUT OA2IN+ OA2IN- OA2OUT OA3IN+⁽³⁾ OA3IN-⁽³⁾ OA3OUT⁽³⁾	I I O I I O I I O	— — — — — — — — —	No No No No No No No No No	Op Amp 1+ input Op Amp 1- input Op Amp 1 output Op Amp 2+ input Op Amp 2- input Op Amp 2 output Op Amp 3+ input Op Amp 3- input Op Amp 3 output
PGD1 PGC1 PGD2 PGC2 PGD3 PGC3	I/O I I/O I I/O I	ST ST ST ST ST ST	No No No No No No	Data I/O pin for Programming/Debugging Communication Channel 1 Clock input pin for Programming/Debugging Communication Channel 1 Data I/O pin for Programming/Debugging Communication Channel 2 Clock input pin for Programming/Debugging Communication Channel 2 Data I/O pin for Programming/Debugging Communication Channel 3 Clock input pin for Programming/Debugging Communication Channel 3
MCLR	I/P	ST	No	Master Clear (Reset) input. This pin is an active-low Reset to the device.
AV_DD	P	P	No	Positive supply for analog modules. This pin must be connected at all times.
AV_SS	P	P	No	Ground reference for analog modules. This pin must be connected at all times.
V_DD	P	—	No	Positive supply for peripheral logic and I/O pins. This pin must be connected at all times.
V_SS	P	—	No	Ground reference for logic and I/O pins. This pin must be connected at all times.
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power  ST = Schmitt Trigger input with CMOS levels O = Output I = Input   PPS = Peripheral Pin Select TTL = TTL input buffer Note: Not all pins are available in all package variants. See the Pin Diagrams section for pin availability. PWM4L and PWM4H pins are available on PPS.