36 MOSFET Gate Driver Electrical Characteristics

Table 36-1. **Absolute Maximum Ratings^(†)**
Parameter			Rating
Input Voltage, HV_DD			(GND – 0.3V) to +40V
Internal Power Dissipation			Internally Limited
Operating Junction Temperature⁽²⁾			-40°C to +165°C
Transient Junction Temperature⁽¹⁾			+170°C
Storage Temperature⁽²⁾			-55°C to +165°C
Digital I/O			-0.3V to 5.5V
Low-Voltage Analog I/O			-0.3V to 5.5V
VBx, WAKE			(GND – 0.3V) to +40V
PHx, HSx			(GND – 5.5V) to +40V
VBOOT, LSx.			(GND – 0.3V) to +13.2V
CAP1, CAP2			(GND – 0.3V) to +40V
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability. Note: Transient junction temperatures should not exceed one second in duration. Sustained junction temperatures above +170°C may impact the device reliability. The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air (i.e., T_A, T_J, θJA). Exceeding the maximum allowable power dissipation may cause the device operating junction temperature to exceed the maximum +165°C rating. Sustained junction temperatures above +165°C can impact the device reliability.).

Table 36-2. AC/DC Characteristics
Electrical Specifications: Unless otherwise noted: T_J = -40°C to +150°C; typical values are for +25°C, HV_DD = 13.5V, CV_BOOT = 4.7 μF, CV_REG = 4.7 μF, C_CP = 220 nF.
Parameters	Symbol	Min	Typ	Max	Units	Conditions
Power Supply Input
Input Operating Voltage	HV_DD	4.5	—	40	V	V_REG active
Input Operating Voltage	HV_DD	6.0	—	29.0	V	Driver output active
Input Supply Current	I_SUP	—	5	15	µA	Sleep mode, T_J = +25°C
		—	180	330		Standby, OE = 0V
		—	500	—		Active, HV_DD > 13, 5V, OE > VDIG_HI_TH
		—	1200	—		Active, HV_DD = 6V, T_J = +25°C
Input Supply Current	I_SUP	—	5	15	µA	Sleep mode, T_J = +25°C
		—	200	350		Standby, OPAMP = 1, OE = 0V
		—	800	1300		Standby, OPAMP = 0, OE = 0V
		—	1000	—		Active, HV_DD > 13, 5V, OE > V_{DIG_HI_TH}
		—	1500	—		Active, OE > V_{DIG_HI_TH}, HV_DD = 7V, TJ = +25°C
Bias Generator
+12V Regulated Charge Pump (V_BOOT)
Charge Pump Current	I_CP	20	—	—	mA	HV_DD = 9.0V
Charge Pump Start	CP_START	12.50	12.75	—	V	Falling
Charge Pump Stop	CP_STOP	—	13.25	14	V	Rising
Charge Pump Frequency	CP_FSW	—	76.80	—	kHz	HV_DD = 9.0V
Charge Pump Frequency	CP_FSW	—	0	—	kHz	HV_DD = 14V
Charge Pump Switch Resistance	CP_RDSON	—	14	—	W	RDSON sum of high side and low side⁽¹⁾
Output Voltage	V_BOOT	—	12	—	V	HV_DD ≥ 14V, I_OUT = 30 mA
		9	12	—		7V ≤ HV_DD < 14V, C_CP = 150 nF, I_OUT = 20 mA
		9	—	—		6.25V ≤ HV_DD < 7V, C_CP = 270 nF, I_OUT = 15 mA
Output Voltage Tolerance	\|TOLV_OUT12\|	—	—	4.0	%	I_OUT = 30 mA
Output Capability	I_BOOT	30	—	—	mA	Average current
Output Current Limit	I_BOOTLIMIT	50	60	80	mA	Average current
Output Voltage Temperature Coefficient	TCV_OUT12	—	160	—	ppm/°C	Note 1
Line Regulation	\|ΔV_OUT/ (V_OUT x Δ)\|	—	0.1	0.5	%/V	14V < HV_DD < 19V, I_OUT = 30 mA
Load Regulation	ΔV_OUT/V_OUT\|	—	0.2	1.0	%	I_OUT = 0.1 mA to 30 mA, HV_DD = 14V
Power Supply Rejection Ratio	PSRR	—	60	—	dB	f = 1 kHz, IOUT = 10 mA⁽¹⁾
Output Capacitor Capacitance Range	CV_BOOT	4.7	—	10	µF	Ceramic, Tantalum, Electrolytic⁽¹⁾
Output Capacitor ESR Range	CESR_VBOOT	0.010	—	1.0	W	Note 1
Flying Capacitor Capacitance Range	C_CP	100	220	1000	nF	Note 1
V_BOOT Ready Threshold	V12sm_pg	—	50	—	%Vboot	State machine V_BOOT Power Good threshold to move to next state ⁽¹⁾
+3.3V Linear Regulator (VREG)
Output Voltage	V_REG	—	—	—	V	HV_DD = 6V, I_OUT = 70 mA
Output Voltage	V_REG	3.168	3.3	3.432	V	V_REG = 3.3V
Output Voltage Tolerance	\|TOLV_REG\|	—	—	4.0	%	—
Output Current	I_OUT	70	—	—	mA	Average current
Output Foldback Current Corner	I_FOLD	80	95	120	mA	Average current
Output Foldback Current Limit	I_{FOLD_LIM}	—	10	—	mA	R_LOAD= 10 mW
Line Regulation	\|ΔV_OUT/ (V_OUT x ΔV_DD)\|	—	0.1	0.5	%/V	V_REG = 3.3V: 6V < H_VDD < 19V, IOUT = 70 mA; V_REG = 5V: 7.5V < HV_DD < 19V, I_OUT = 70 mA
Load Regulation	\|ΔV_OUT/V_OUT\|	—	0.2	1.0	%	_IOUT = 0.1 mA to 70 mA
Power Supply Rejection Ratio	PSRR	—	60	—	dB	f = 1 kHz, I_OUT = 10 mA ⁽¹⁾
Output Capacitor Capacitance Range	CV_REG	4.7	—	30	µF	Ceramic, Tantalum, Electrolytic⁽¹⁾
Output Capacitor ESR Range	CESR_VREG	0.010	—	1.0	W	Note 1
Voltage Supervisor
V_REG Undervoltage Fault Inactive	VREGUV_FINACT	—	92	—	%V_REG	V_REG rising
V_REG Undervoltage Fault Active	VREGUV_FACT	—	88	—	%V_REG	V_REG falling
V_REG Undervoltage Fault Hysteresis	VREGUV_FHYS	—	4	—	%V_REG	—
HV_DD Undervoltage Lockout Inactive	UVLO_INACT	—	6.0	6.25	V	Rising
HV_DD Undervoltage Lockout Active	UVLO_ACT	5.1	5.5	—	V	Falling
HV_DD Undervoltage Lockout Hysteresis	UVLO_HYS	—	0.5	—	V	—
HV_DD Undervoltage Shutdown Active	UVSHDN_ACT	4.0	4.25	4.5	V	HV_DD < UVSHDN_ACT
HV_DD Undervoltage Shutdown Inactive	UVSHDN_INACT	UVLO_INACT			V	HV_DD > UVLO_INACT
HV_DD Overvoltage Lockout Active	OVLOACT	—	32.0	33.0	V	HV_DD rising
HV_DD Overvoltage Lockout Inactive	OVLO_INACT	29.0	30.0	—	V	HV_DD falling
HV_DD Overvoltage Lockout Hysteresis	OVLO_HYS	—	2.0	—	V	—
Temperature Supervisor
Thermal Warning Temperature	T_WARN	—	140	—	°C	Rising temperature
Thermal Warning Hysteresis	DT_WARN	—	15	—	°C	Falling temperature
Thermal Shutdown Temperature	T_SD	170	210	—	°C	Rising temperature⁽¹⁾
Thermal Shutdown Hysteresis	ΔT_SD	—	25	—	°C	Falling temperature
Motor Control Unit
Gate Output Drivers
Output Driver Source Current	I_SOURCE	0.25	0.37	—	A	HS[A:C], LS[A:C] ⁽¹⁾
Output Driver Sink Current	I_SINK	0.3	0.49	—	A	HS[A:C], LS[A:C] ⁽¹⁾
Output Driver Source Resistance	R_DSONSOURCE	—	14	26	W	I_OUT = -10 mA, HS[A:C], LS[A:C]
Output Driver Sink Resistance LS	R_DSONSINKLS	—	14	26	W	I_OUT = 10 mA, LS[A:C]
Output Driver Sink Resistance HS Dynamic	R_DSONSINKHSDYN	—	14	26	W	IOUT = 10 mA, HS[A:C], t < 1 ms
Output Driver Sink Resistance HS	R_DSONSINKHS	—	19	31	W	I_OUT = 10 mA, HS[A:C]
Output Driver Fault Blanking Time (UVLO and OCP); Set in the DRVBL[1:0] bits (CFG2[1:0])	t_BLANK	3900	4400	4900	ns	00 – Default ⁽¹⁾
		2000	2200	2400		`01`⁽¹⁾
		900	1100	1300		`10`⁽¹⁾
		400	550	700		`11`⁽¹⁾
Output Driver UVLO Threshold	V^DUVLO	4	—	4.5	V	Configuration Register 0(bit 3 = 0)
Output Driver PWM Dead Time; Set in the DRVDT[2:0] bits (CFG2[4:2])	t_{PWM_DEAD}	1800	2000	2200	ns	`000` – Default ⁽¹⁾
		1550	1750	1950		`001`⁽¹⁾
		1350	1500	1650		`010`⁽¹⁾
		1100	1250	1400		`011`⁽¹⁾
		900	1000	1150		¹⁰⁰⁽¹⁾
		650	750	900		`101`⁽¹⁾
		450	500	650		`110`⁽¹⁾
		200	250	350		`111`⁽¹⁾
Output Driver Propagation Delay Time On	t_{GATE_PROP_ON}	—	40	80	ns	From PWMxy active to HSx/LSx > 10% ⁽¹⁾
Output Driver Propagation Delay Time Off	t_{GATE_PROP_OFF}	—	40	80	ns	From PWMxy inactive to HSx/LSx < 90% ⁽¹⁾
Output Driver HS Drive Voltage	V_HS	4.5	12	12.5	V	With respect to Phase pin⁽¹⁾
Output Driver LS Drive Voltage	V_ls	4.5	12	12.5	V	With respect to ground ⁽¹⁾
Output Driver Short-Circuit Protection Threshold(High Side: HV_DD – VPHX), (Low Side: VPHX – P_GND); Set in the EXTOC[1:0] bits (CFG0[1:0])	Dsc_thr	0.230	0.250	0.270	V	`00` – Default ⁽¹⁾
		0.470	0.500	0.530		`01`⁽¹⁾
		0.720	0.750	0.780		`10`⁽¹⁾
		0.960	1.000	1.040		`11`⁽¹⁾
Output Driver Short-Circuit Filter Time	T_{SC_DLY}	230	—	600	ns	C_LOAD = 1000 pF, HV_DD = 12V, detection after filtering⁽¹⁾
Filter Time for All Other Faults	T_{FLT_DLY}	1400	—	3600	ns	Note 1
Power-up or Sleep to Standby	t_POWER	—	5	—	ms	IVREG = 70 mA
Standby to Motor Operational	t_MOTOR	—	35	—	µs	OE high-low-high transition < 1 ms Fault clearing pulse⁽¹⁾
		—	5	10	ms	OE low-high transition, Standby state to operational⁽¹⁾
		—	—	16	ms	OE low-high transition, Standby state to operational if VBOOT fails to reach V12sm_pg⁽¹⁾
Fault to Driver Output Turn-Off	T_{FAULT_OFF}	—	—	—	µs	CLOAD = 1000 pF, HVDD = 12V, time after Fault occurs⁽¹⁾
		—	0.420	1.0		XOCP⁽¹⁾
		—	2.4	4.0		OVLO⁽¹⁾
		—	4.2	6.0		All other Faults⁽¹⁾
OE Low to Driver Output Turn-Off	T_{DEL_OFF}	—	3.2	4.0	µs	CLOAD = 1000 pF, HVDD = 12V, time after OE = Low⁽¹⁾
OE Low to Standby State	t_STANDBY	0.9	—	1.35	ms	Time after OE = Low, SLEEP bit = 0
OE Low to Sleep State	t_SLEEP	0.9	—	1.35	ms	Time after OE = Low, SLEEP bit = 1
OE Fault Clearing Pulse	t_{FAULT_CLR}	1	—	900	µs	OE high-low-high transition time
Operational Amplifiers (DSTEMP)
Input Offset Voltage	V_OS	-10	—	+10	mV	V_CM = 0V
Input Offset Temperature Drift	ΔV_OS/ΔT_A	—	±2.0	—	µV/°C	V_CM= 0V⁽¹⁾
Input Bias Current	I_B	-1	—	+1	µA	—
Common-Mode Input Range	V_CMR	-0.3	—	V_REG	V	—
Common-Mode Rejection Ratio	CMRR	—	80	—	dB	Freq = 1 kHz, I_OUT = 10 µA⁽¹⁾
Maximum Output Voltage Range	V_OL, V_OH	0.15	—	VREG – 0.300	V	I_OUT = ±200 µA
Slew Rate	SR	—	±7	—	V/µs	Symmetrical, C_LOAD = 20 pF⁽¹⁾
Gain Bandwidth Product	GBWP	4	10.0	—	MHz	Note 1
I/O Ports
Digital Interface
Digital Input/Output	DIGITAL_I/O	0	—	5.5	V	V_REG = 5.0V version⁽¹⁾
Digital Input/Output	DIGITAL_I/O	0	—	3.3	V	V_REG = 3.3V version⁽¹⁾
Digital Open-Drain Low Voltage	DIGITALV_I/O	—	—	50	mV	I_LOAD = 1 mA
Digital Input Rising Threshold	V_{DIG_HI_TH}	—	—	1.26	V	—
Digital Input Falling Threshold	V_{DIG_LO_TH}	0.54	—	—	V	—
Digital Input Current	I_DIG	—	30	100	µA	V_DIG = 3.0V
Digital Input Current	I_DIG	—	0.2	—	µA	V_DIG = 0V
Input Pull-Down Resistance	R_PULLDN	—	51	—	kΩ	PWM[A:C]H/L, OE pins
Analog Interface
Analog Low-Voltage Input	ANALOG_VIN	0	—	5.5	V	Excludes high-voltage pins⁽¹⁾
Analog Low-Voltage Output	ANALOG_VOUT	0	—	Vreg	V	Excludes high-voltage pins ⁽¹⁾
WAKE Input⁽²⁾
Input Voltage	WAKE_I/O	0	—	HVdd	V	—
Input Rising Threshold	V_{WAKE_HI_TH}	—	—	1.26	V	Note 1
Input Falling Threshold	V_{WAKE_LO_TH}	0.54	—	—	V	—
Input Current	I_WAKE	—	0.2	—	µA	VWAKE = 0.0V ⁽¹⁾
		—	70	—		VWAKE = 3.3V ⁽¹⁾
		—	106	—		VWAKE = 5.0V ⁽¹⁾
		—	596	—		VWAKE = 28V ⁽¹⁾
Input Pull-Down Resistance	R_{WAKE_PULLDN}	—	51	—	kW	—
WAKE Signal Setup Time	t_{WAIT_SETUP}	150	—	—	µs	Minimum time WAKE pin must be logic high before triggering wake-up
DE2 Communications
Baud Rate	BAUD	9030	9600	10170	bps	Half-duplex
Power-up Delay	PU_DELAY	—	6	10	ms	Time from rising HV_DD ≥ 6V to DE2 starts sending POR message, CV_REG = 1 µF ⁽¹⁾
DE2 Sink Current	I_{DE2_SINK}	1	—	—	mA	V_DE2 ≤ 50 mV ⁽¹⁾
DE2 Message Response Time	t_{DE2_RSP}	0	—	1	ms	Time from last received Stop bit to response Start bit
DE2 Host Wait Time	t_{DE2_WAIT}	2.8	—	—	ms	Minimum time for host to wait for response; three packets based on 9600 Baud
DE2 Message Receive Time-out	DE2_RCVTOUT	—	—	1.45	ms	Time after Start bit received to NACK for no Stop bit
Auto-Baud Detection Window (Break)	ABAUD_DET	1.29	—	2.00	ms	Window for valid detection of continuous logic low on DE2 link
Auto-Baud Response Delay	ABAUD_DLY	—	1.00	—	ms	Delay from ABAUDDET to start of sending 0x55 byte
Auto-Baud Complete Delay	ABAUD_COMP	—	2.00	—	ms	Delay after sending 0x55 byte before exiting auto-baud function
Delay Between Bytes of Multibyte Message from Host	t_{DE2_HOST_ MULTI_DLY}	—	—	1.3	ms	Delay between message bytes arriving from host
Note: Limits based on design, simulation or characterization. Not production tested. The WAKE pin must remain high for > t_{WAIT_SETUP} time to successfully awaken the device from Sleep.