37 LIN Transceiver Electrical Characteristics

Table 37-1. Absolute Maximum Ratings⁽¹⁾
Parameter	Rating
Input Voltage, LIN_V_DD	(LIN_V_SS – 0.3V) to +40.0V
Logic Pins (LIN_RXD, LIN_TXD, LIN_EN) Voltage Levels	-0.3V to +5.5V
Logic Output DC Currents	-5 mA to +5 mA
LIN_BUS DC Voltage	-27V to +40V
LIN_BUS DC Voltage Transient (Pulse Time <500 ms)	-27V to +43V
LIN_BUS DC Current	200 mA
LIN_INH DC Voltage	-0.3V to (LIN_VDD + 0.3V)
LIN_INH DC Current	-100 mA to +30 mA
LIN_WKIN DC Voltage	-0.3V to +40V
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Table 37-2. Electrical Characteristics
Parameters	Test Conditions	Pin	Symbol	Min.	Typ.	Max.	Unit	Type
Operating Conditions (unless otherwise stated): 5V < V_S < 28V, -40°C < T_J < +150°C; all values refer to LIN_V_SS pins
LIN_V_DD Pin
Nominal DC Voltage Range		LIN_VDD	V_S	5	13.5	28	V	A
Supply Current in Sleep Mode	Sleep mode, V_LIN> V_S– 0.5V, V_S< 14V, T = +27°C	LIN_V_DD	I_VSsleep	3	9	15	µA	B
	Sleep mode,V_LIN> V_S– 0.5V, V_S< 14V	LIN_V_DD	I_VSsleep	3	11	20	µA	A
	Sleep mode, V_LIN= 0V, bus shorted to LIN_VSS, V_S< 14V	LIN_V_DD	I_{VSsleep_short}	20	50	100	µA	A
Supply Current in Normal Mode	Bus recessive, V_S< 14V	LIN_V_DD	I_VSrec	150	250	320	µA	A
Supply Current in Normal Mode	Bus dominant (internal LIN pull-up resistor active),V_S< 14V	LIN_VDD	I_VSdom	200	700	950	µA	A
Supply Current in Fail-Safe Mode	Bus recessive, V_S< 14V	LIN_V_DD	I_VSfail	40	80	110	µA	A
LIN_VDD Undervoltage Threshold (switching from Normal to Fail-Safe mode)	Decreasing supply voltage	LIN_V_DD	V_{VS_th_N_F_down}	3.9	4.3	4.7	V	A
	Increasing supply voltage	LIN_V_DD	V_{VS_th_N_F_up}	4.1	4.6	4.9	V	A
LIN_V_DD Undervoltage Hysteresis		LIN_V_DD	V_{VS_hys_F_N}	0.1	0.25	0.4	V	A
LIN_V_DDOperation Threshold (switching to Unpowered mode)	Switch to Unpowered mode	LIN_V_DD	V_{VS_th_U_down}	1.9	2.05	2.3	V	A
LIN_V_DDOperation Threshold (switching to Unpowered mode)	Switch from Unpowered mode to Fail-Safe mode	LIN_VDD	V_{VS_th_U_F_up}	2.0	2.25	2.4	V	A
LIN_V_DDUndervoltage Hysteresis		LIN_V_DD	V_{VS_hys_U}	0.1	0.2	0.3	V	A
LIN_RXD Output Pin (open-drain)
Low-Level Output Sink Capability	Normal mode, V_LIN= 0V, I_RXD= 2 mA	LIN_RXD	V_RXDL	—	0.2	0.4	V	A
High-Level Leakage Current	Normal mode, V_LIN= V_S, V_RXD= 5V	LIN_RXD	I_RXDH	-3	—	+3	µA	A
LIN_TXD Input/Output Pin
Low-Level Voltage Input		LIN_TXD	V_TXDL	-0.3	—	+0.8	V	A
High-Level Voltage Input		LIN_TXD	V_TXDH	2	—	5.5	V	A
Pull-Down Resistor	V_TXD= 5V	LIN_TXD	R_TXD	150	200	300	kW	A
Low-Level Leakage Current	V_TXD= 0V	LIN_TXD	I_TXD	-3	—	+3	µA	A
Low-Level Output Sink Current at Wake-up Request	Fail-Safe mode, V_TXD= 0.4V	LIN_RXD	I_TXD	2	2.5	8	mA	A
LIN_EN Input Pin
Low-Level Voltage Input		LIN_EN	V_ENL	-0/3	—	+0.8	V	A
High-Level Voltage Input		LIN_EN	V_ENH	2	—	5.5	V	A
Pull-Down Resistor	V_EN= 5V	LIN_EN	R_EN	50	125	200	kW	A
Low-Level Input Current	V_EN= 0V	LIN_EN	I_EN	-3	—	+3	µA	A
LIN_WKIN Input Pin
High-Level Input Voltage		LIN_WKIN	V_WKinH	V_S– 1V	—	V_S+ 0.3V	V	A
Low-Level Input Voltage	Initializes a wake-up signal	LIN_WKIN	V_WKinL	-1	—	V_S– 3.3V	V	A
LIN_WKIN Pull-up Current	V_S< 28V, V_WKin= 0V	LIN_WKIN	I_WKin	-30	-10	—	µA	A
High-Level Leakage Current	V_S= 28V, V_WKin= 28V	LIN_WKIN	I_WKinL	-5	—	+5	µA	A
Debounce Time of Low Pulse for Wake-up via LIN_WKIN	V_WKin= 0V	LIN_WKIN	t_WKin	50	100	150	µs	A
LIN_INH Output Pin
Switch-on Resistance Between LIN_V_DD and LIN_INH	Normal or Fail-Safe mode, I_INH= -15 mA	LIN_INH	R_DSon,INH	—	12	25	W	A
Leakage Current	Transceiver in Sleep mode, V_INH= 0V/28V, V_S= 28V	LIN_INH	I_leak,INH	-3	—	+3	µA	A
High-Level Voltage	Normal or Fail-Safe mode, I_INH= -15 mA	LIN_INH	V_INH	V_S– 0.375	—	V_S	V	A
LIN Bus Driver: Bus Load Conditions:Load 1 (small): 1 nF, 1 kW; Load 2 (large): 10 nF, 500W; External Pull-up, R_RXD= 4.7 kW; C_RXD= 20 pF; Load 3 (medium): 6.8 nF, 660W characterized on samples. Duty Cycle 1 and Duty Cycle 2 specify the timing parameters for proper operation at 20 kb/s and Duty Cycle 3 and Duty Cycle 4 at 10.4 kb/s.
Driver Recessive Output Voltage	Load1/Load2	LIN_BUS	V_BUSrec	0.9 x V_S	—	V_S	V	A
Driver Dominant Voltage	V_VS= 7V, R_load= 500W	LIN_BUS	V_LoSUP	—	—	1.2	V	A
Driver Dominant Voltage	V_VS= 18V, R_load= 500W	LIN_BUS	V_HiSUP	—	—	2	V	A
Driver Dominant Voltage	V_VS= 7V, R_load= 1000W	LIN_BUS	V_{LoSUP_1k}	0.6	—	—	V	A
Driver Dominant Voltage	V_VS= 18V, R_load= 1000W	LIN_BUS	V_{HiSUP_1k}	0.8	—	—	V	A
Pull-up Resistor to LIN_V_DD	Serial diode is mandatory	LIN_BUS	R_LIN	20	30	47	kW	A
Voltage Drop at the Serial Diodes	In pull-up path with R_slave, I_SerDiode = 10 mA	LIN_BUS	V_SerDiode	0.4	—	1.0	V	D
LIN_BUS Current Limitation	V_BUS = V_{Bat_max}	LIN_BUS	I_{BUS_LIM}	40	120	200	mA	A
Input Leakage Current at the Receiver Including Pull-up Resistor as Specified	Input leakage current driver off, V_BUS= 0V, V_BAT= 12V	LIN_BUS	I_{BUS_PAS_dom}	-1	-0.35	—	mA	A
Leakage Current LIN_BUS Recessive	Driver off, 8V < V_BAT< 18V, 8V < V_BUS< 18V, V_BUS >V_BAT	LIN_BUS	I_{BUS_PAS_rec}	—	10	20	µA	A
Leakage Current when Control Unit Disconnected from Ground;Loss of Local Ground must not Affect Communication in the Residual Network	GND_Device = V_S, V_BAT = 12V, 0V < V_BUS< 18V	LIN_BUS	I_{BUS_NO_gnd}	-10	+0.5	+10	µA	A
Leakage Current at Disconnected Battery; Node has to Sustain the Current that can Flow Under this Condition; Bus Must Remain Operational Under this Condition	V_BATdisconnected, V_{SUP_Device}= LIN_VSS, 0V < V_BUS< 18V	LIN_BUS	I_{BUS_NO_bat}	—	0.1	2	µA	A
Capacitance on Pin LIN_BUS to LIN_V_SS		LIN_BUS	C_LIN	—	—	20	pF	D
LIN Bus Receiver
Center of Receiver Threshold	V_{BUS_CNT} = (V_{th_dom} + V_{th_rec})/2	LIN_BUS	V_{BUS_CNT}	0.475 x V_S	0.5 x V_S	0.525 x V_S	V	A
Receiver Dominant State	V_EN= 5V	LIN_BUS	V_BUSdom	-27	—	0.4 x V_S	V	A
Receiver Recessive State	V_EN= 5V	LIN_BUS	V_BUSrec	0.6 x V_S	—	40	V	A
Receiver Input Hysteresis	V_hys = V_{th_rec} – V_{th_dom}	LIN_BUS	V_BUShys	0.028 x V_S	0.1 x V_S	0.175 x V_S	V	A
Pre-Wake Detection LIN_BUS High-Level Input Voltage		LIN_BUS	V_LINH	V_S– 2V	—	V_S+ 0.3V	V	A
Pre-Wake Detection LIN_BUS Low-Level Input Voltage	Activates the LIN receiver	LIN_BUS	V_LINL	-27	—	V_S– 3.3V	V	A
Internal Timers
Dominant Time for Wake-up via LIN_BUS	V_LIN= 0V	LIN_BUS	t_bus	50	100	150	µs	A
Time Delay for Mode Change from Fail-Safe into Normal Mode viaLIN_EN Pin	V_EN= 5V	LIN_EN	t_norm	5	15	20	µs	A
Time Delay for Mode Change from Normal Mode to Sleep Mode via LIN_EN Pin	V_EN= 0V	LIN_EN	t_sleep	5	15	20	µs	A
Time Delay for Mode Change from Sleep Mode to Normal Mode via LIN_EN Pin	V_EN= 5V	LIN_EN	t_{s_norm}	—	150	300	µs	A
LIN_TXD Dominant Time-out Time	V_TXD= 0V	LIN_TXD	t_dom	20	40	60	ms	A
Duty Cycle 1	TH_Rec(max)= 0.744 x V_S, TH_Dom(max)= 0.581 x V_S, V_S= 7.0V to 18V, t_Bit= 50 µs, D1 = t_{bus_rec} (min) / (2 x t_Bit)	LIN_BUS	D1	0.396	—	—	—	A
Duty Cycle 2	TH_Rec(min)= 0.422 x V_S, TH_Dom(min)= 0.284 x V_S, V_S= 7.6V to 18V, t_Bit= 50 µs, D2 = t_{bus_rec} (max) / (2 x t_Bit)	LIN_BUS	D2	—	—	0.581	—	A
Duty Cycle 3	TH_Rec(max)= 0.778 x V_S, TH_Dom(max)= 0.616 x V_S, V_S= 7.0V to 18V, t_Bit= 96 µs, D3 = t_{bus_rec} (min) / (2 x t_Bit)	LIN_BUS	D3	0.417	—	—	—	A
Duty Cycle 4	TH_Rec(max)= 0.778 x V_S, TH_Dom(max)= 0.616 x V_S, V_S= 7.0V to 18V, t_Bit= 96 µs, D4 = t_{bus_rec} (max) / (2 x t_Bit)	LIN_BUS	D4	—	—	0.590	—	A
Slope Time Falling and Rising Edge at LIN_BUS	V_S= 7.0V to 18V	LIN_BUS	t_{SLOPE_fall,}t_{SLOPE_rise}	3.5	—	22.5	µs	A
Receiver Electrical AC Parameters of the LIN Physical Layer;LIN Receiver, LIN_RXD Load Conditions: C_RXD= 20 pF, R_RXD= 4.7 kW
Propagation Delay of Receiver	V_S= 7.0V to 18V, t_{rx_pd} = max(_{trx_pdr}, t_{rx_pdf})	LIN_RXD	t_{rx_pd}	—	—	6	µs	A
Symmetry of Receiver Propagation Delay Rising Edge Minus Falling Edge	V_S = 7.0V to 18V, t_{rx_sym} = t_{rx_pdr} – t_{rx_pdf}	LIN_RXD	t_{rx_sym}	-2	—	+2	µs	A
Legend: Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design Parameter

Figure 37-1. Definition of LIN Bus Timing Characteristics