28 Operational Amplifier

Note: Some device variants support only two op amp instances. Refer to Table   1 and Table 28-1 for availability.
Table 28-1. Op Amp Availability
Package TypeOp Amps
28-pin1, 2
36-pin1, 2, 3
48-pin1, 2, 3
64-pin1, 2, 3

The dsPIC33CDVL256MC506 family implements three instances of operational amplifiers (op amps). The op amps can be used for a wide variety of purposes, including signal conditioning and filtering. The three op amps are functionally identical. The block diagram for a single amplifier is shown in Figure 28-1 .

Figure 28-1. Single Operational Amplifier Block Diagram

The op amps are controlled by two SFR registers: AMPCON1L and AMPCON1H. They remain in a Low-Power state until the AMPON bit is set. Each op amp can then be enabled independently by setting the corresponding AMPENx bit (x = 1, 2, 3).

The NCHDISx bit provides some flexibility regarding input range versus Integral Nonlinearity (INL). When NCHDISx = 0 (default), the op amps have a wider input voltage range (see AC Characteristics and Timing Parameters). When NCHDISx = 1, the wider input range is traded for improved INL performance (lower INL).