14.6.2.7 Changing the Clock Frequency
The selected source for a Generator can be divided by writing a division value in the Division Factor bit field of the Generator Control register (GENCTRLn.DIV). How the actual division factor is calculated is depending on the Divide Selection bit (GENCTRLn.DIVSEL).
If GENCTRLn.DIVSEL= 0 and GENCTRLn.DIV is either 0 or 1, the output clock will be undivided.
Note: The number of
available DIV bits may vary from Generator to Generator.