26.5.10.4.2 Reads From Memory
Upon reads in memory, if FLTCTRL.FLTEN = 1 and FLTCTRL.FLTMD is set to single fault injection on reads (FLTCTRL.FLTMD = 0x4) or double fault injection for reads (FLTCTRL.FLTMD =0x5), and a read is performed at the address defined in FFLTADR.FLTADR, the fault injection logic will then corrupt 1 or 2 bits in the 72-bit vector. The corruption happens after reading in memory and before syndrome and SECOUT computation.
When fault injection or capture is enabled in FLTCTRL.FLTMD and FLTEN, then FFLTCAP, FFLTPAR and FFLTSYN will only be updated when a SEC or DED error is found in the 72-bit vector available after the ‘fault injection on reads’ logic and before the potential ‘correction by the ECC’ logic. In case a SEC or DED is found:
- FFLTPAR.SECIN shows the ECC bits of this 72-bit vector (note that these ECC bits may have been corrupted on purpose by the fault injection on writes and/or on reads)
- FFLTPAR.SECOUT shows the ECC bits computed again on the 64 data bits of this 72-bit vector (note that these data bits may have been corrupted on purpose by the fault injection on writes and/or on reads)
- FFLTCAP.FLTADR contains the address of the corrupted word
- In case of a single error:
- INTFLAG.SERR is set if SECCNT = 0
- INTFLAG.FLTCAP are set and FFLTSYN.DERRSERR = 0x1
- FFLTSYN.SECSYN provides the syndrome, which indicates which bit of the 72-bit vector has been corrupted. The look-up table below gives the correspondence between the syndrome value and the corresponding corrupted bit.
- FFLTSYN, FFLTCAP, and FFLTPAR registers will be populated with the information related to this SEC error and locked until either INTFLAG.SERR and INTFLAG.FLTCAP are cleared and a new SEC error is logged, or a DED error occurs. Only then will the registers be updated.
- In case of a double error:
- INTFLAG.SERR, INTFLAG.DERR, INTFLAG.FLTCAP are set and FFLTSYN.DERRSERR 0x2 or 0x3
- FFLTSYN, FFLTCAP, and FFLTPAR registers will be populated with the information related to this DED error and locked until INTFLAG.SERR, INTFLAG.DERR and INTFLAG.FLTCAP are cleared and a new SEC or DED error is logged. Only then will the registers be updated.
| SECSYN Value | Faulty Bit | SECSYN Value | Faulty Bit | SECSYN Value | Faulty Bit |
|---|---|---|---|---|---|
| 0x23 | D[0] | 0x19 | D[24] | 0xC8 | D[48] |
| 0x43 | D[1] | 0x1A | D[25] | 0xD0 | D[49] |
| 0x83 | D[2] | 0x1C | D[26] | 0xE0 | D[50] |
| 0x3D | D[3] | 0xE9 | D[27] | 0x4F | D[51] |
| 0x45 | D[4] | 0x2A | D[28] | 0x51 | D[52] |
| 0x85 | D[5] | 0x2C | D[29] | 0x61 | D[53] |
| 0x89 | D[6] | 0x4C | D[30] | 0x62 | D[54] |
| 0x49 | D[7] | 0x4A | D[31] | 0x52 | D[55] |
| 0x46 | D[8] | 0x32 | D[32] | 0x91 | D[56] |
| 0x86 | D[9] | 0x34 | D[33] | 0xA1 | D[57] |
| 0x07 | D[10] | 0x38 | D[34] | 0xC1 | D[58] |
| 0x7A | D[11] | 0xD3 | D[35] | 0x9E | D[59] |
| 0x8A | D[12] | 0x54 | D[36] | 0xA2 | D[60] |
| 0x0B | D[13] | 0x58 | D[37] | 0xC2 | D[61] |
| 0x13 | D[14] | 0x98 | D[38] | 0xC4 | D[62] |
| 0x92 | D[15] | 0x94 | D[39] | 0xA4 | D[63] |
| 0x8C | D[16] | 0x64 | D[40] | 0x01 | ECC[0] |
| 0x0D | D[17] | 0x68 | D[41] | 0x02 | ECC[1] |
| 0x0E | D[18] | 0x70 | D[42] | 0x04 | ECC[2] |
| 0xF4 | D[19] | 0xA7 | D[43] | 0x08 | ECC[3] |
| 0x15 | D[20] | 0xA8 | D[44] | 0x10 | ECC[4] |
| 0x16 | D[21] | 0xB0 | D[45] | 0x20 | ECC[5] |
| 0x26 | D[22] | 0x31 | D[46] | 0x40 | ECC[6] |
| 0x25 | D[23] | 0x29 | D[47] | 0x80 | ECC[7] |