42.7.10 Synchronization Status

Name: SYNCBUSY
Offset: 0x10
Reset: 0x00000000
Property: Read-Only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
        CC1 
Access R 
Reset 0 
Bit 76543210 
 CC0COUNTFILTERPRESCSTATUSCTRLBENABLESWRST 
Access RRRRRRRR 
Reset 00000000 

Bits 7, 8 – CC Compare Channel x Synchronization Busy

This bit is cleared when the synchronization of Compare Channel x (CCx) register between the clock domains is complete.

This bit is set when the synchronization of Compare Channel x (CCx) register between clock domains is started.

Bit 6 – COUNT Count Synchronization Busy

This bit is cleared when the synchronization of Count register between the clock domains is complete.

This bit is set when the synchronization of Count register between clock domains is started.

Bit 5 – FILTER Filter Synchronization Busy

This bit is cleared when the synchronization of Filter register between the clock domains is complete.

This bit is set when the synchronization of Filter register between clock domains is started.

This bit is always read '0' when COUNTER operation mode is selected.

Bit 4 – PRESC Prescaler Synchronization Busy

This bit is cleared when the synchronization of Prescaler register between the clock domains is complete.

This bit is set when the synchronization of Prescaler register between clock domains is started.

Bit 3 – STATUS Status Synchronization Busy

This bit is cleared when the synchronization of Status register between the clock domains is complete.

This bit is set when the synchronization of Status register between clock domains is started.

Bit 2 – CTRLB Control B Synchronization Busy

This bit is cleared when the synchronization of Control B register between the clock domains is complete.

This bit is set when the synchronization of Control B register between clock domains is started.

Bit 1 – ENABLE Enable Synchronization Busy

This bit is cleared when the synchronization of Enable register bit between the clock domains is complete.

This bit is set when the synchronization of Enable register bit between clock domains is started.

Bit 0 – SWRST Software Reset Synchronization Busy

This bit is cleared when the synchronization of Software Reset register bit between the clock domains is complete.

This bit is set when the synchronization of Software Reset register bit between clock domains is started.