1.3.5 Fabric_Debug

The following figure shows the IP blocks inside the Fabric_Debug block.

Figure 1-3. Fabric_Debug Overall Design Blocks

The Fabric_Debug block demonstrates the following FPGA fabric debug features of SmartDebug.

  • FPGA array debugging capabilities using a counter that loads a counting pattern into the DPSRAM instance. The data value of the DPSRAM block is the same as the address value of the block. On the read side of the DPSRAM, a count checker (count_chk) ensures that the count progresses as expected. The output (error) is driven high if there is an error.
  • µPROM debugging feature of SmartDebug using a µPROM instance.
  • Live probes to monitor an internal user-selected point on the device in real-time, and how to set active probes for dynamic, asynchronous read and write to a flip-flop or probe point. These features help to quickly observe the output of the logic internally or experiment to determine how the logic is affected by writing to a probe point.
  • Capabilities to read and modify fabric SRAM content in real-time.

µPROM: This is the embedded non-volatile PROM arranged in a single row at the bottom of the fabric and is read-only through the fabric interface. µPROM is programmed with the FPGA bitstream during fabric programming. µPROM stores the initialization data for DPSRAM and µSRAM and other user data. μPROM is initiated with the uprom.mem file.

µSRAM: This is the fabric RAM block that is accessed using the PF_SRAM_AHBL_AXI IP. Generally, µSRAM is initialized with a user application executable at device power-up. In the example design, µSRAM is initialized with the sram.hex file.