40.7.10 Event Control

Table 40-19. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	EVCTRL
Offset:	0x20
Reset:	0x00000000
Property:	RW


Bit	31	30	29	28	27	26	25	24
	MCEO[7:0]
Access
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	MCEI[7:0]
Access
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	TCEI[1:0]		TCINV[1:0]			CNTEO	TRGEO	OVFEO
Access
Reset	0	0	0	0		0	0	0


Bit	7	6	5	4	3	2	1	0
	CNTSEL[1:0]		EVACT1[2:0]			EVACT0[2:0]
Access
Reset	0	0	0	0	0	0	0	0

Bits 31:24 – MCEO[7:0] Match or Capture Channel x Event Output Enable

Bits 23:16 – MCEI[7:0] Match or Capture Channel x Event Input Enable

Bits 15:14 – TCEI[1:0] Timer/counter Event x Input Enable

Bits 13:12 – TCINV[1:0] Inverted Event x Input Enable

Bit 10 – CNTEO Timer/counter Output Event Enable

This bit is used to enable the counter cycle event. When enabled, an event will be generated on begin or end of counter cycle depending of on EVCTRL.CNTSEL(EVCTRL<7:6>) settings.

Value	Description
0	Counter cycle output event is disabled and will not be generated.
1	Counter cycle output event is enabled and will be generated depending on EVCTRL.CNTSEL(EVCTRL<7:6>) value.

Bit 9 – TRGEO Retrigger Output Event Enable

This bit is used to enable the counter retrigger event. When enabled, an event will be generated when the counter retriggers operation.

Value	Description
0	Counter retrigger event is disabled and will not be generated.
1	Counter retrigger event is enabled and will be generated for every counter retrigger.

Bit 8 – OVFEO Overflow/Underflow Output Event Enable

This bit is used to enable the overflow/underflow event. When enabled an event will be generated when the counter reaches the TOP or the ZERO value.

Value	Description
0	Overflow/underflow counter event is disabled and will not be generated.
1	Overflow/underflow counter event is enabled and will be generated for every counter overflow/underflow.

Bits 7:6 – CNTSEL[1:0] Timer/counter Output Event Mode

These bits define on which part of the counter cycle the counter event output is generated.

Value	Name	Description
0	START	An interrupt/event is generated when a new counter cycle starts
1	END	An interrupt/event is generated when a counter cycle ends
2	BETWEEN	An interrupt/event is generated when a counter cycle ends, except for the first and last cycles
3	BOUNDARY	An interrupt/event is generated when a new counter cycle starts or a counter cycle ends

Bits 5:3 – EVACT1[2:0] Timer/counter Input Event1 Action

These bits define the action the TCC will perform on TCE1 event input.

Value	Name	Description
0	OFF	Event action disabled
1	RETRIGGER	Re-trigger counter on event
2	DIR	Direction control
3	STOP	Stop counter on event
4	DEC	Decrement counter on event
5	PPW	Period capture value in CC0 register, pulse width capture value in CC1 register
6	PWP	Period capture value in CC1 register, pulse width capture value in CC0 register
7	FAULT	Non-recoverable fault

Bits 2:0 – EVACT0[2:0] Timer/counter Input Event0 Action

These bits define the action the TCC will perform on TCE0 event input 0.

Value	Name	Description
0	OFF	Event action disabled
1	RETRIGGER	Start, restart or re-trigger counter on event
2	COUNTEV	Count on event
3	START	Start counter on event
4	INC	Increment counter on event
5	COUNT	Count on active state of asynchronous event
6	STAMP	Stamp capture
7	FAULT	Non-recoverable fault