40.7.1 Control A

Table 40-8. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	CTRLA
Offset:	0x00
Reset:	0x00000000
Property:	RW


Bit	31	30	29	28	27	26	25	24
	CPTEN[7:0]
Access
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	DMAOS							FCYCLE
Access
Reset	0							0


Bit	15	14	13	12	11	10	9	8
	MSYNC	ALOCK	PRESCSYNC[1:0]		RUNSTDBY	PRESCALER[2:0]
Access
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
		RESOLUTION[1:0]					ENABLE	SWRST
Access
Reset		0	0				0	0

Bits 31:24 – CPTEN[7:0] Capture Channel x Enable

Bit 23 – DMAOS DMA One-shot Trigger Mode

Bit 16 – FCYCLE Full Cycle

Bit 15 – MSYNC Master Synchronization (only for TCC Slave Instance)

Bit 14 – ALOCK Auto Lock

Bits 13:12 – PRESCSYNC[1:0] Prescaler and Counter Synchronization Selection

Value	Name	Description
0	GCLK	Reload or reset counter on next GCLK
1	PRESC	Reload or reset counter on next prescaler clock
2	RESYNC	Reload or reset counter on next GCLK and reset prescaler counter

Bit 11 – RUNSTDBY Run in Standby

Bits 10:8 – PRESCALER[2:0] Prescaler

Value	Name	Description
0	DIV1	No division
1	DIV2	Divide by 2
2	DIV4	Divide by 4
3	DIV8	Divide by 8
4	DIV16	Divide by 16
5	DIV64	Divide by 64
6	DIV256	Divide by 256
7	DIV1024	Divide by 1024

Bits 6:5 – RESOLUTION[1:0] Enhanced Resolution

Value	Name	Description
0	NONE	Dithering is disabled
1	DITH4	Dithering is done every 16 PWM frames
2	DITH5	Dithering is done every 32 PWM frames
3	DITH6	Dithering is done every 64 PWM frames

Bit 1 – ENABLE Enable

Bit 0 – SWRST Software Reset

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