40.7.3 Control B Set
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CTRLBSET |
| Offset: | 0x05 |
| Reset: | 0x00 |
| Property: | RW |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CMD[2:0] | IDXCMD[1:0] | ONESHOT | LUPD | DIR | |||||
| Access | |||||||||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 7:5 – CMD[2:0] TCC Command
These bits can be used for software control of re-triggering and stop commands of the TCC. When a command has been executed, the CMD bit field will be read back as zero. The commands are executed on the next prescaled GCLK_TCCx clock cycle.
Writing zero to this bit group has no effect
Writing a valid value to this bit group will set the associated command.
| Value | Name | Description |
|---|---|---|
| 0 | NONE | No action |
| 1 | RETRIGGER | Clear start, restart or retrigger |
| 2 | STOP | Force stop |
| 3 | UPDATE | Force update or double buffered registers |
| 4 | READSYNC | Force COUNT read synchronization |
| 5 | DMAOS | One-shot DMA trigger |
Bits 4:3 – IDXCMD[1:0] Ramp Index Command
These bits can be used to force cycle A and cycle B changes in all RAMP2x operations. On timer/counter update condition, the command is executed, the IDX flag in STATUS register is updated and the IDXCMD command is cleared.
Writing a zero to these bits has no effect.
Writing a valid value to these bits will set a command.
| Value | Name | Description |
|---|---|---|
| 0 | DISABLE | Command disabled: Index toggles between cycles A and B |
| 1 | SET | Set index: cycle B will be forced in the next cycle |
| 2 | CLEAR | Clear index: cycle A will be forced in the next cycle |
| 3 | HOLD | Hold index: the next cycle will be the same as the current cycle |
Bit 2 – ONESHOT One-Shot
This bit controls one-shot operation of the TCC. When in one-shot operation, the TCC will stop counting on the next overflow/underflow condition or a stop command.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will enable the one-shot operation.
| Value | Description |
|---|---|
| 0 | The TCC will count continuously. |
| 1 | The TCC will stop counting on the next underflow/overflow condition. |
Bit 1 – LUPD Lock Update
This bit controls the update operation of the TCC buffered registers.
When CTRLBSET.LUPD (CTRLBSET<1>) is set, the hardware UPDATE registers with value from their buffered registers is disabled. Disabling the update ensures that all buffer registers are valid before an hardware update is performed. After all the buffer registers are loaded correctly, the buffered registers can be unlocked.
This bit has no effect when input capture operation is enabled.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will disable the registers updates on hardware UPDATE condition.
| Value | Description |
|---|---|
| 0 | The CCBUFy, PERBUF buffer register bitfields are copied into the corresponding CCy, PER registers and register bitfields on hardware update condition. |
| 1 | The CCBUFy, PERBUF buffer registers bitfields are not copied into the corresponding CCy, PER registers and register bitfields on hardware update condition. |
Bit 0 – DIR Counter Direction
This bit is used to change the direction of the counter.
Writing a '0' to this bit has no effect
Writing a '1' to this bit will set the bit and make the counter count down. Reading this bit gives following status:
| Value | Description |
|---|---|
| 0 | The timer/counter is counting up (incrementing). |
| 1 | The timer/counter is counting down (decrementing). |