46.3 Power Supply

Table 46-6. Power Supply DC Electrical Specifications
DC CHARACTERISTICS			Standard Operating Conditions: VDDREG = VDDIO = AVDD 1.71V to 3.63V (unless otherwise stated) Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
Param. No.	Symbol	Characteristics	Min.	Typ.	Max.	Units	Conditions
REG_5	VDDIO_CIN ⁽⁴⁾	VDDIO Input Bypass parallel Capacitor pair	33	—	—	µF	Bulk Ceramic or solid Tantalum with ESR <0.5Ω ⁽⁵⁾
REG_5	VDDIO_CIN ⁽⁴⁾	VDDIO Input Bypass parallel Capacitor pair	100	—	—	nF	Ceramic X7R with ESR <0.5Ω on all VDDIOx pins ⁽⁵⁾
REG_6	VDDREG_CIN⁽⁴⁾	VDDREG Input Bypass parallel Capacitor pair	33	—	—	µF	Bulk Ceramic or solid Tantalum with ESR <0.5Ω ⁽⁵⁾
REG_6	VDDREG_CIN⁽⁴⁾	VDDREG Input Bypass parallel Capacitor pair	100	—	—	nF	Ceramic X7R with ESR <0.5Ω on all VDDIOx pins ⁽⁵⁾
REG_15	USERLDO_COUT	User LDO output capacitor	10	—	—	uF	Ceramic X7R with ESR <0.5Ω
REG_17	AVDD_CIN ⁽⁴⁾	AVDD Input Bypass parallel Capacitor pair	10	—	—	µF	Bulk Ceramic or solid Tantalum with ESR <0.5Ω
REG_17	AVDD_CIN ⁽⁴⁾	AVDD Input Bypass parallel Capacitor pair	100	—	—	nF	Ceramic X7R with ESR <0.5Ω
REG_23	AVDD_LEXT⁽¹⁾	AVDD series Ferrite Bead DCR (DC Resistance)	—	—	0.1	Ω	≥600 Ohms @ 100 MHz
REG_25	AVDD_LEXT⁽¹⁾	Ferrite Bead current Rating	500	—	—	mA	—
REG_37	VDDIO ⁽²⁾	VDDIO Input Voltage Range	1.71	3.3	3.63	V	—
REG_39	AVDD⁽²⁾	AVDD Input Voltage Range	1.71	3.3	3.63	V	—
REG_40	VDDREG ⁽³⁾	VDDREG Input Voltage Range	1.71	3.3	3.63	V	—
REG_43	SVDD_R	VDDIO/AVDD/VDDREG Rise Ramp Rate to Ensure Internal Power-on Reset Signal	0.00000033	—	0.33	V/µs	Failure to meet this specification may lead to start-up or unexpected behaviors
REG_45	VPOR	Power-on Reset	1.44	1.5	1.59	V	VDD Power-down
REG_47	VDDIO / AVDD BOR ⁽⁵⁾	VDDIO / AVDD Brown-out Reset Thresholds	(*)	—	(*)	V	BOR_TRIP_VDDx = 0x0 HYST_BOR_VDDx = 0x0
			(*)	—	(*)	V	BOR_TRIP_VDDx = 0x1 HYST_BOR_VDDx = 0x0
			(*)	—	(*)	V	BOR_TRIP_VDDx = 0x2 HYST_BOR_VDDx = 0x0
			(*)	—	(*)	V	BOR_TRIP_VDDx = 0x3 HYST_BOR_VDDx = 0x0
			(*)	—	(*)	V	BOR_TRIP_VDDx = 0x0 HYST_BOR_VDDx = 0x1
			(*)	—	(*)	V	BOR_TRIP_VDDx = 0x1 HYST_BOR_VDDx = 0x1
			(*)	—	(*)	V	BOR_TRIP_VDDx = 0x2 HYST_BOR_VDDx = 0x1
			(*)	—	(*)	V	BOR_TRIP_VDDx = 0x3 HYST_BOR_VDDx = 0x1
REG_49	VDDREG BOR ⁽⁵⁾	VDDREG Brown-out Reset Thresholds	(*)	—	(*)	V	HYST_BOR_VDDREG = 0x0 ⁽⁶⁾
REG_49	VDDREG BOR ⁽⁵⁾	VDDREG Brown-out Reset Thresholds	(*)	—	(*)	V	HYST_BOR_VDDREG = 0x1 ⁽⁶⁾
REG_51	VDDIO / AVDD / VDDREG DCBOR ⁽⁷⁾	VDDIO / AVDD / VDDREG Duty Cycled BOR Thresholds	1.43	—	1.75	V	BOR_TRIP = 0x0 BOR_HYS = 0x0
			1.87	—	2.28	V	BOR_TRIP = 0x1 BOR_HYS = 0x0
			2.22	—	2.75	V	BOR_TRIP = 0x2 BOR_HYS = 0x0
			2.43	—	3.01	V	BOR_TRIP = 0x3 BOR_HYS = 0x0
			1.4	—	1.75	V	BOR_TRIP = 0x0 BOR_HYS = 0x1
			1.81	—	2.28	V	BOR_TRIP = 0x1 BOR_HYS = 0x1
			2.13	—	2.75	V	BOR_TRIP = 0x2 BOR_HYS = 0x1
			2.27	—	3.01	V	BOR_TRIP = 0x3 BOR_HYS = 0x1
REG_52	LVD⁽⁸⁾	VDDIO Low Voltage Detector Thresholds	(*)	—	(*)	V	LVD.LEVEL = 0x0
			(*)	—	(*)	V	LVD.LEVEL = 0x1
			(*)	—	(*)	V	LVD.LEVEL = 0x2
			(*)	—	(*)	V	LVD.LEVEL = 0x3
			(*)	—	(*)	V	LVD.LEVEL = 0x4
			(*)	—	(*)	V	LVD.LEVEL = 0x5
			(*)	—	(*)	V	LVD.LEVEL = 0x6
			(*)	—	(*)	V	LVD.LEVEL = 0x7
			(*)	—	(*)	V	LVD.LEVEL = 0x8
			(*)	—	(*)	V	LVD.LEVEL = 0x9
			(*)	—	(*)	V	LVD.LEVEL = 0xA
			(*)	—	(*)	V	LVD.LEVEL = 0xB
			(*)	—	(*)	V	LVD.LEVEL = 0xC
			(*)	—	(*)	V	LVD.LEVEL = 0xD
			(*)	—	(*)	V	LVD.LEVEL = 0xE
			(*)	—	(*)	V	LVD.LEVEL = 0xF
REG_53	TRST	External RESET valid active pulse width	2	—	—	µs	Minimum reset active time to guarantee MCU reset
Note: Ferrite Bead ISAT(min) ≥ (IDDANA(max) * 1.15). VDDREG voltage must be equal or lower than VDDIO. VDDIO and AVDD must be at the same voltage level. All bypass caps should be located immediately adjacent to pins and on the same side of the PCB as the MCU. Each primary power supply group VDDIO, AVDD , VDDREG should have one bulk capacitor and all power pins everywhere a 100 nF bypass cap. Voltages below the minimum BOR threshold will result in a device reset, except for the BOR_VDDUSB that can cause an interrupt. Voltages above the maximum BOR threshold will allow the device starting-up. Overall functional device operation at VBORMIN < VDD < VDDMIN is guaranteed, but not characterized. Device will function with degraded performances below VDDMIN. Voltages below the minimum DCBOR threshold will result in a device reset. Voltages below the minimum LVD threshold will result in a falling detection. Voltages above the maximum LVD threshold will result in a rising detection. Enabling the LVD when VDDIO is between the minimum or maximum threshold may result in unexpected behavior.