35.10.5 System Clock

Table 35-14. System Clock Timing Characteristics
Symbol Description Min. Typ. ✝ Max. Unit Conditions
fCLK_MAIN Main clock frequency, industrial temperature range(1) 0 5 MHz

-40°C ≤ TA ≤ +85°C

VDD ≥ 1.8V

0 10 MHz

-40°C ≤ TA ≤ +85°C

VDD ≥ 2.7V

0 20 MHz

-40°C ≤ TA ≤ +85°C

VDD ≥ 4.5V

Main clock frequency, extended temperature range(1) 0 8 MHz

-40°C ≤ TA ≤ +125°C

VDD ≥ 2.7V

0 16 MHz

-40°C ≤ TA ≤ +125°C

VDD ≥ 4.5V

fCY Instruction clock frequency fCLK_MAIN MHz
TCY Instruction period(2) 41.6 1/fCY ns

Data in the “Typ.” column is at TA = 25°C and VDD = 3.0V unless otherwise specified. These parameters are not tested and are for design guidance only.

Note:
  1. The main clock frequency (CLK_MAIN) is configured by the Clock Select (CLKSEL) bit field, as described in the CLKCTRL - Clock Controller section.
  2. Instruction Cycle Period (TCY) is equal to the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type, under standard operating conditions with the device executing code. Exceeding these specified limits may result in incorrect code execution and/or higher than expected current consumption. All devices are tested to operate at ‘min’ values with an external clock applied to the EXTCLK pin. When using an external clock input, the ‘max’ cycle time limit is ‘DC’ (no clock) for all devices.