4.2 Two-Wire Interface
- Serial Program Clock (PGECx)
- Serial Program Data (PGEDx)
These signals are described in the following two sections. Refer to the specific device data sheet for the connection of the signals to the chip pins.
Device Pin Name | Programmer Pin Name | Pin Type | Pin Description |
---|---|---|---|
MCLR | MCLR | Power | Programming enable |
ENVREG(2) | N/A | Input | Enable for on-chip voltage regulator |
VDD, VDDIO, VBAT(2) and AVDD(1) | VDD | Power | Power supply |
VDDCORE(2) and VDDR1V8(2) | N/A | Power | Power supply for DDR interface |
VSS, VSS1V8(2) and AVSS(1) | VSS | Power | Ground |
VCAP(2) | N/A | Power | CPU logic filter capacitor connection |
PGECx | PGEC | Input | Primary programming pin pair:
|
PGEDx | PGED | Input/Output | Primary programming pin pair:
|
Note:
|
For more details on the connection of the signals to the device pins, refer to the specific device data sheet.
Serial Program Clock (PGECx)
PGECx is the clock that controls the updating of the TAP controller and the shifting of data through the Instruction or selected Data registers. PGECx is independent of the processor clock, with respect to both frequency and phase.
Serial Program Data (PGEDx)
PGEDx is the data input/output to the Instruction or selected Data Registers, it is also the control signal for the TAP controller. This signal is sampled on the falling edge of the PGECx for some TAP controller states.