48.19 Analog-to-Digital Converter (ADC) Electrical Specifications

Table 48-25. ADC AC Electrical Specifications
AC CHARACTERISTICS			Standard Operating Conditions: VDDREG = VDDIO = AVDD 1.71V to 3.63V (unless otherwise stated) Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
Param. No.	Symbol	Characteristics	Min.	Typ.	Max.	Units	Conditions
Device Supply
ADC_1	AVDD	ADC Module Supply	AVDD (min.)	—	AVDD (max.)	V	VDDIOx = AVDD
Reference Inputs
ADC_3	VREF⁽¹⁾	ADC Reference Voltage	2.4	—	AVDD	V	VREF ≤ AVDD
Analog Input Range
ADC_7	AFS	Full-Scale Analog Input Signal Range	AVSS	—	VREF	V	Single-Ended mode
ADC_7	AFS	Full-Scale Analog Input Signal Range	-VREF	—	+VREF	V	Differential mode, VCMIN = VREF/2
ADC_9	VCMIN	Input Common Mode voltage	—	VREF/2	—	V	—
Note: ADC functional device operation with either internal or external VREF <2.4V is functional, but not characterized. ADC will function, but with degraded accuracy of approximately ~((0.06 * 2n)/VREF) LSB’s over full scale range, where "n" = #bits. ADC accuracy is limited by internal VREF accuracy and drift, MCU generated noise and users application noise/accuracy on AVDD and AVSS.

Table 48-26. ADC Single-Ended Mode AC Electrical Specifications
AC CHARACTERISTICS			Standard Operating Conditions: VDDREG = VDDIO = AVDD 1.71V to 3.63V (unless otherwise stated) Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
Param. No.	Symbol	Characteristics	Min.	Typ.	Max.	Units	Conditions
Single-Ended Mode ADC Accuracy⁽⁴⁾
SADC_11	Res	Resolution	8	—	12	bits	Selectable 8-bit, 10-bit, and 12- bit resolution ranges
SADC_13	INL⁽³⁾	Integral Nonlinearity	-2.2	-1.7/1.1	1.3	LSB	4.5 Msps,Iinternal VREF = AVDD = VDDIO = 3.3V
SADC_19	DNL⁽³⁾	Differential Nonlinearity	-1.4	-1/1.8	2.4	LSB	4.5 Msps, Internal VREF = AVDD = VDDIO = 3.3V
SADC_25	GERR ^(3,6)	Gain Error	-4.7	—	-1.2	LSB	4.5 Msps, Internal VREF = AVDD = VDDIO = 3.3V
SADC_31	EOFF^(3,6)	Offset Error	1.9	—	5.1	LSB	4.5 Msps, Internal VREF = AVDD = VDDIO = 3.3V
Single-Ended Mode ADC Dynamic Performance^(1,2,4)
SADC_43	ENOB ⁽³⁾	Effective Number of bits	10.3	10.75	—	bits	VREF = AVDD = VDDIO = 3.3V at 12 bit at 4.5 Msps Slew rate control enabled on IOs (slewlim > 0)
SADC_45	SINAD ^(1,2,3)	Signal-to-Noise and Distortion	63	66	—	dB
SADC_47	SNR ^(1,2,3)	Signal-to-Noise ratio	64	66	—
SADC_51	THD ^(1,2,3,5)	Total Harmonic Distortion	—	-81	-77
Note: Characterized with an analog input sine wave = (FTP (max.) / 100). Example: FTP (max.) = 1 Msps/100 = 10 kHz sine wave. Sine wave peak amplitude = 96% ADC_ Full Scale amplitude input with 12-bit resolution. ADC is configured in 12 bits mode, All registers are at the reset default value unless otherwise stated, and XOSC48M AGC is ON (i.e., XOSCCTRLA.AGC = 0x1). ADC functional device operation with either internal or external VREF < 2.4V is functional, but not characterized. ADC will function, but with degraded accuracy of approximately ~((0.06 * 2n) / VREF) LSB’s over full scale range, where "n" = #bits. ADC accuracy is limited by internal VREF accuracy + drift, MCU generated noise plus users application noise/accuracy on VDDANA, GNDANA. Value taken over 7 harmonics.

Table 48-27. ADC Differential Mode AC Electrical Specifications
AC CHARACTERISTICS			Standard Operating Conditions: VDDREG = VDDIO = AVDD 1.71V to 3.63V (unless otherwise stated) Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
Param. No.	Symbol	Characteristics	Min.	Typ.	Max.	Units	Conditions
Differential Mode ADC Accuracy⁽⁴⁾
DADC_11	Res	Resolution	8	—	12	bits	Selectable 8-bit, 10-bit, and 12-bit resolution ranges
DADC_13	INL⁽³⁾	Integral Nonlinearity	-2.3	-1.6/1.5	2.2	LSB	4.5 Msps, Internal VREF = AVDDA = VDDIO = 3.3V
DADC_19	DNL ⁽³⁾	Differential Nonlinearity	-1	-1/1.9	2.7	LSB	4.5 Msps, Internal VREF = AVDDA = VDDIO = 3.3V
DADC_25	GERR ^(3,6)	Gain Error	-4.3	—	0	LSB	4.5 Msps, Internal VREF = AVDDA = VDDIO = 3.3V
DADC_31	EOFF ^(3,6)	Offset Error	-0.1	—	1.9	LSB	4.5 Msps, Internal VREF = AVDDA = VDDIO = 3.3V
Differential Mode ADC Dynamic Performance^(1,2,4)
DADC_43	ENOB ⁽³⁾	Effective Number of bits	10.5	11.25	—	bits	VREF = AVDD = VDDIO = 3.3V at 12 bit at 4.5 Msps
DADC_45	SINAD ^{(1, 2, 3)}	Signal-to-Noise and Distortion	65	69	—	dB
DADC_47	SNR ^{(1, 2, 3)}	Signal-to-Noise ratio	65	69	—
DADC_51	THD ^{(1, 2, 3, 5)}	Total Harmonic Distortion	—	-86	-80
Note: Characterized with an analog input sine wave = (FTP (max.) / 100). Example: FTP (max.) = 1 Msps / 100 = 10 kHz sine wave. Sine wave peak amplitude = 96% ADC_ Full Scale amplitude input with 12-bit resolution. ADC is configured in 12 bits mode, All registers are at the reset default value unless otherwise stated, and XOSC48M AGC is ON (i.e., XOSCCTRLA.AGC = 0x1). ADC functional device operation with either internal or external VREF < 2.4V is functional, but not characterized. ADC will function, but with degraded accuracy of approximately ~((0.06 * 2n) / VREF) LSB’s over full scale range, where "n" = #bits. ADC accuracy is limited by internal VREF accuracy and drift, MCU generated noise and users application noise/accuracy on VDDANA, GNDANA. Value taken over 7 harmonics.

Table 48-28. ADC Conversion and Sample AC Electrical Specifications
AC CHARACTERISTICS			Standard Operating Conditions: VDDREG = VDDIO = AVDD 1.71V to 3.63V (unless otherwise stated) Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
Param. No.	Symbol	Characteristics	Min.	Typ.	Max.	Units	Conditions
ADC Clock Requirements
ADC_53	TAD	ADC Clock Period	13.88	—	7145	ns	VREF = AVDD = 3.3V and Res = 6,8,10 bit
ADC_53	TAD	ADC Clock Period	13.88	—	1250	ns	VREF = AVDD = 3.3V and Res = 12 bit
ADC_55	fGCLK_ADCx	ADCx module GCLK max input frequency	—	—	FCLK_51	MHz	VREF = AVDD = 3.3V
ADC Throughput Rates
ADC_57	FTPR⁽¹⁾	Sample-Rate for ADC0 with SAMC = 0 (min.)	—	—	4.5	Msps	12-bit resolution, Resource Impedance ≤ 200 Ω
			—	—	5.14		10-bit resolution, Rsource Impedance ≤ 350 Ω
			—	—	6		8-bit resolution, Rsource Impedance ≤ 500 Ω
			—	—	7.2		6-bit resolution, Rsource Impedance ≤ 650 Ω
ADC Conversion and Sample time
ADC_59	TSAMP	Sample-Time for ADC0	3	—	—	TAD	12 bit TAD (min.), Ext Analog Input Rsource ≤ 200 Ω, (max) ADC Clock
			3	—	—		10 bit TAD (min.), Ext Analog Input Rsource ≤ 350 Ω, (max) ADC Clock
			8	—	—		12 bit TAD (min.), Ext Analog Input Rsource ≤ 500 Ω, (max) ADC Clock
			8	—	—		10 bit TAD (min.), Ext Analog Input Rsource ≤ 700 Ω, Max ADC Clock
			14	—	—		12 bit TAD (min.), Ext Analog Input Rsource ≤ 1 kΩ, max ADC Clock
			14	—	—		10 bit TAD (min.), Ext Analog Input Rsource ≤ 1.25 kΩ, (max) ADC Clock
			64	—	—		12 bit TAD (min), Ext Analog Input Rsource ≤ 5 kΩ, (max) ADC Clock
			64	—	—		10 bit TAD (min), Ext Analog Input Rsource ≤ 5.5 kΩ, (max) ADC Clock
ADC_61	TCNV	Conversion Time (after sample time is complete)	13			TAD	12-bit resolution
			11				10-bit resolution
			9				8-bit resolution
			7				6-bit resolution
ADC_63	Twarm-up	Warm Up Time after CTRLA.ANAEN = 1 and CTRLA.ENABLE = 1	—	—	500 TAD or 20 µs, whichever is bigger	µs	—
Note: ADC Throughput Rate FTP = ((1 / ((TSAMP + TCNV) * TAD)) / (Number of user active analog inputs in use on specific target ADC module)). Specification values assume only one AINx channel in use.