16.7.8 ECC Control REGISTER
| Name: | ECCCTRL |
| Offset: | 0x884 |
| Reset: | 0x00000070 |
| Property: | R/W |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| SECCNT[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ECCUNLCK | ECCCTL[1:0] | ||||||||
| Access | R/K | R/W | R/W | ||||||
| Reset | 1 | 1 | 1 | ||||||
Bits 15:8 – SECCNT[7:0] SECCNT is the start value of an internal counter that decrements (by 1 per panel reporting an SEC) its count value each time an SEC occurs on a flash access (including the CTL[2:0] bits if in Dynamic ECC Mode). The internal counter stops decrementing at zero. If an SEC error occurs when the internal counter is zero, the SERR flag bit is set. This field counts all SEC errors and is not limited to SEC errors on unique addresses.
Bit 6 – ECCUNLCK The read value dictates the unlock state.
Note: This field can only be modified
when ECCUNLCK=1.
The read value dictates the unlock state:
| Value | Name | Description |
|---|---|---|
| 1 | UNLOCKED | ECCUNLCK and ECCCTL[1:0] can be written |
| 0 | LOCKED | ECCUNLCK and ECCCTL[1:0] cannot be written |
Bits 5:4 – ECCCTL[1:0] Condition: {PFM_PNL_DATA_MSB==71} 10 (ECC) = Reserved - Resolves to STRICT 01 (DYNAMIC) = Reserved - Resolves to STRICT Note: This field can only be modified when ECCUNLCK=1
Restricts one or more NVMOPs:
| Value | Name | Description |
|---|---|---|
| 3 | DISABLE | ECC Writes with No Error Check Reads |
| 0 | STRICT | ECC Writes with ECC Reads |
| 3 | DISABLE | Dynamic Writes with No Error Check Reads |
| 2 | ECC | ECC Writes with Dynamic Reads (NVMOP = Single Program Operation disabled) |
| 1 | DYNAMIC | Dynamic Writes with Dynamic Reads |
| 0 | STRICT | ECC Writes with ECC Reads (NVMOP = Single Program Operation disabled) |