16.7.4 Write Control Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | PAC_WRCTRL_H2PB1 |
| Offset: | 0x848 |
| Reset: | 0x0000_002E |
| Property: | R/P |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| KEY[7:0] | |||||||||
| Access | R/P | R/P | R/P | R/P | R/P | R/P | R/P | R/P | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PERID[7:0] | |||||||||
| Access | R/P | R/P | R/P | R/P | R/P | R/P | R/P | R/P | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
Bits 23:16 – KEY[7:0] Peripheral Access Control Key
These bits define the peripheral access control key:
others = reserved
Note:
- Always read 0’s.
- Bits 7-2 are ignored and may be unimplemented.
| Value | Name | Description |
|---|---|---|
| 0x3 | LOCK | Set and Lock the write protection state of the peripheral until the next reset |
| 0x2 | SET | Set the peripheral write protection |
| 0x1 | CLEAR | Clear the peripheral write protection |
| 0x0 | OFF | No Action |
Bits 7:0 – PERID[7:0] Peripheral Identifier
The PERID represents the peripheral whose control is changed using the WRCTRL.KEY. The Peripheral Identifier is provided by the chip spec and corresponds to the PERID[7:0]. For INTFLAGn.PERIDm, STATUSn.PERIDm, and LOCKn.PERIDm, n=PERID/32 and m=PERID%32.
Note:
- Always read 0’s.
- Bits 7 is ignored and may be unimplemented.