RXELM3 and TXELM3 bits are only present when FIFODEPTH = 8 or higher.
RXELM4 and TXELM4 bits are only present when FIFODEPTH = 16 or higher.
RXELM5 and TXELM5 bits are only present when FIFODEPTH = 32.
Legend: HSC = Hardware Settable/Clearable bit
Name:
SPIxSTATH
Offset:
0x2B6, 0x2D2,
0x2EE
Bit
15
14
13
12
11
10
9
8
RXELM[5:0]
Access
R/HSC
R/HSC
R/HSC
R/HSC
R/HSC
R/HSC
Reset
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
TXELM[5:0]
Access
R/HSC
R/HSC
R/HSC
R/HSC
R/HSC
R/HSC
Reset
0
0
0
0
0
0
Bits 13:8 – RXELM[5:0]
Receive Buffer Element Count bits (valid in Enhanced Buffer
mode)(1,2,3)
Bits 5:0 – TXELM[5:0]
Transmit Buffer Element Count bits (valid in Enhanced Buffer
mode)(1,2,3)
DS70005452D
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
