6.2 Register Summary


Offset	Name	Bit Pos.	7	6	5	4	3	2	1	0
0x00 ... 0x03	Reserved
0x04	CSI_N_LANES	31:24
		23:16
		15:8
		7:0								N_LANES
0x08	CSI_CSI2_RESETN	31:24
		23:16
		15:8
		7:0								CSI2_RESETN
0x0C	CSI_INT_ST_MAIN	31:24
		23:16							STATUS_INT_PKT	STATUS_INT_DPHY
		15:8
		7:0						STATUS_INT_FRAME_FATAL	STATUS_INT_PKT_FATAL	STATUS_INT_PHY_FATAL
0x10	CSI_DATA_IDS_1	31:24	DI3_VC[1:0]		DI3_DT[5:0]
		23:16	DI2_VC[1:0]		DI2_DT[5:0]
		15:8	DI1_VC[1:0]		DI1_DT[5:0]
		7:0	DI0_VC[1:0]		DI0_DT[5:0]
0x14	CSI_DATA_IDS_2	31:24	DI7_VC[1:0]		DI7_DT[5:0]
		23:16	DI6_VC[1:0]		DI6_DT[5:0]
		15:8	DI5_VC[1:0]		DI5_DT[5:0]
		7:0	DI4_VC[1:0]		DI4_DT[5:0]
0x18 ... 0x3F	Reserved
0x40	CSI_PHY_SHUTDOWNZ	31:24
		23:16
		15:8
		7:0								PHY_SHUTDOWNZ
0x44	CSI_DPHY_RSTZ	31:24
		23:16
		15:8
		7:0								DPHY_RSTZ
0x48	CSI_PHY_RX	31:24
		23:16							PHY_RXCLKACTIVEHS	PHY_RXULPSSCLKNOT
		15:8
		7:0							PHY_RXULPSESC_1	PHY_RXULPSESC_0
0x4C	CSI_PHY_STOPSTATE	31:24
		23:16								PHY_STOPSTATECLK
		15:8
		7:0							PHY_STOPSTADATA_1	PHY_STOPSTADATA_0
0x50	CSI_PHY_TEST_CTRL0	31:24
		23:16
		15:8
		7:0							PHY_TESTCLK	PHY_TESTCLR
0x54	CSI_PHY_TEST_CTRL1	31:24
		23:16								PHY_TESTEN
		15:8	PHY_TESTDOUT[7:0]
		7:0	PHY_TESTDIN[7:0]
0x58 ... 0xCB	Reserved
0xCC	CSI_PHY_CAL	31:24
		23:16
		15:8
		7:0								RXSKEWCALHS
0xD0 ... 0xDF	Reserved
0xE0	CSI_INT_ST_PHY_FATAL	31:24
		23:16
		15:8
		7:0							PHY_ERRSOTSYNCHS_1	PHY_ERRSOTSYNCHS_0
0xE4	CSI_INT_MSK_PHY_FATAL	31:24
		23:16
		15:8
		7:0							MASK_ERRSOTSYNCHS_1	MASK_ERRSOTSYNCHS_0
0xE8	CSI_INT_FORCE_PHY_FATAL	31:24
		23:16
		15:8
		7:0							FORCE_ERRSOTSYNCHS_1	FORCE_ERRSOTSYNCHS_0
0xEC ... 0xEF	Reserved
0xF0	CSI_INT_ST_PKT_FATAL	31:24
		23:16								ERR_ECC_DOUBLE
		15:8
		7:0					VC3_ERR_CRC	VC2_ERR_CRC	VC1_ERR_CRC	VC0_ERR_CRC
0xF4	CSI_INT_MSK_PKT_FATAL	31:24
		23:16								MASK_ERR_ECC_DOUBLE
		15:8
		7:0					MASK_VC3_ERR_CRC	MASK_VC2_ERR_CRC	MASK_VC1_ERR_CRC	MASK_VC0_ERR_CRC
0xF8	CSI_INT_FORCE_PKT_FATAL	31:24
		23:16								FORCE_ERR_ECC_DOUBLE
		15:8
		7:0					FORCE_VC3_ERR_CRC	FORCE_VC2_ERR_CRC	FORCE_VC1_ERR_CRC	FORCE_VC0_ERR_CRC
0xFC ... 0xFF	Reserved
0x0100	CSI_INT_ST_FRAME_FATAL	31:24
		23:16					ERR_FRAME_DATA_VC3	ERR_FRAME_DATA_VC2	ERR_FRAME_DATA_VC1	ERR_FRAME_DATA_VC0
		15:8					ERR_F_SEQ_VC3	ERR_F_SEQ_VC2	ERR_F_SEQ_VC1	ERR_F_SEQ_VC0
		7:0					ERR_F_BNDRY_MATCH_VC3	ERR_F_BNDRY_MATCH_VC2	ERR_F_BNDRY_MATCH_VC1	ERR_F_BNDRY_MATCH_VC0
0x0104	CSI_INT_MSK_FRAME_FATAL	31:24
		23:16					MASK_ERR_FRAME_DATA_VC3	MASK_ERR_FRAME_DATA_VC2	MASK_ERR_FRAME_DATA_VC1	MASK_ERR_FRAME_DATA_VC0
		15:8					MASK_ERR_F_SEQ_VC3	MASK_ERR_F_SEQ_VC2	MASK_ERR_F_SEQ_VC1	MASK_ERR_F_SEQ_VC0
		7:0					MASK_ERR_F_BNDRY_MATCH_VC3	MASK_ERR_F_BNDRY_MATCH_VC2	MASK_ERR_F_BNDRY_MATCH_VC1	MASK_ERR_F_BNDRY_MATCH_VC0
0x0108	CSI_INT_FORCE_FRAME_FATAL	31:24
		23:16					FORCE_ERR_FRAME_DATA_VC3	FORCE_ERR_FRAME_DATA_VC2	FORCE_ERR_FRAME_DATA_VC1	FORCE_ERR_FRAME_DATA_VC0
		15:8					FORCE_ERR_F_SEQ_VC3	FORCE_ERR_F_SEQ_VC2	FORCE_ERR_F_SEQ_VC1	FORCE_ERR_F_SEQ_VC0
		7:0					FORCE_ERR_F_BNDRY_MATCH_VC3	FORCE_ERR_F_BNDRY_MATCH_VC2	FORCE_ERR_F_BNDRY_MATCH_VC1	FORCE_ERR_F_BNDRY_MATCH_VC0
0x010C ... 0x010F	Reserved
0x0110	CSI_INT_ST_PHY	31:24
		23:16							PHY_ERRESC_1	PHY_ERRESC_0
		15:8
		7:0							PHY_ERRSOTHS_1	PHY_ERRSOTHS_0
0x0114	CSI_INT_MSK_PHY	31:24
		23:16							MASK_PHY_ERRESC_1	MASK_PHY_ERRESC_0
		15:8
		7:0							MASK_PHY_ERRSOTHS_1	MASK_PHY_ERRSOTHS_0
0x0118	CSI_INT_FORCE_PHY	31:24
		23:16							FORCE_PHY_ERRESC_1	FORCE_PHY_ERRESC_0
		15:8
		7:0							FORCE_PHY_ERRSOTHS_1	FORCE_PHY_ERRSOTHS_0
0x011C ... 0x011F	Reserved
0x0120	CSI_INT_ST_PKT	31:24
		23:16					VC3_ERR_ECC_CORRECTED	VC2_ERR_ECC_CORRECTED	VC1_ERR_ECC_CORRECTED	VC0_ERR_ECC_CORRECTED
		15:8
		7:0					ERR_ID_VC3	ERR_ID_VC2	ERR_ID_VC1	ERR_ID_VC0
0x0124	CSI_INT_MSK_PKT	31:24
		23:16					MASK_VC3_ERR_ECC_CORRECTED	MASK_VC2_ERR_ECC_CORRECTED	MASK_VC1_ERR_ECC_CORRECTED	MASK_VC0_ERR_ECC_CORRECTED
		15:8
		7:0					MASK_ERR_ID_VC3	MASK_ERR_ID_VC2	MASK_ERR_ID_VC1	MASK_ERR_ID_VC0
0x0128	CSI_INT_FORCE_PKT	31:24
		23:16					FORCE_VC3_ERR_ECC_CORRECTED	FORCE_VC2_ERR_ECC_CORRECTED	FORCE_VC1_ERR_ECC_CORRECTED	FORCE_VC0_ERR_ECC_CORRECTED
		15:8
		7:0					FORCE_ERR_ID_VC3	FORCE_ERR_ID_VC2	FORCE_ERR_ID_VC1	FORCE_ERR_ID_VC0
0x012C ... 0x012F	Reserved
0x0130	CSI_INT_ST_LINE	31:24
		23:16	ERR_L_SEQ_DI7	ERR_L_SEQ_DI6	ERR_L_SEQ_DI5	ERR_L_SEQ_DI4	ERR_L_SEQ_DI3	ERR_L_SEQ_DI2	ERR_L_SEQ_DI1	ERR_L_SEQ_DI0
		15:8
		7:0	ERR_L_BNDRY_MATCH_DI7	ERR_L_BNDRY_MATCH_DI6	ERR_L_BNDRY_MATCH_DI5	ERR_L_BNDRY_MATCH_DI4	ERR_L_BNDRY_MATCH_DI3	ERR_L_BNDRY_MATCH_DI2	ERR_L_BNDRY_MATCH_DI1	ERR_L_BNDRY_MATCH_DI0
0x0134	CSI_INT_MSK_LINE	31:24
		23:16	MASK_ERR_L_SEQ_DI7	MASK_ERR_L_SEQ_DI6	MASK_ERR_L_SEQ_DI5	MASK_ERR_L_SEQ_DI4	MASK_ERR_L_SEQ_DI3	MASK_ERR_L_SEQ_DI2	MASK_ERR_L_SEQ_DI1	MASK_ERR_L_SEQ_DI0
		15:8
		7:0	MASK_ERR_L_BNDRY_MATCH_DI7	MASK_ERR_L_BNDRY_MATCH_DI6	MASK_ERR_L_BNDRY_MATCH_DI5	MASK_ERR_L_BNDRY_MATCH_DI4	MASK_ERR_L_BNDRY_MATCH_DI3	MASK_ERR_L_BNDRY_MATCH_DI2	MASK_ERR_L_BNDRY_MATCH_DI1	MASK_ERR_L_BNDRY_MATCH_DI0
0x0138	CSI INT_FORCE_LINE	31:24
		23:16	FORCE_ERR_L_SEQ_DI7	FORCE_ERR_L_SEQ_DI6	FORCE_ERR_L_SEQ_DI5	FORCE_ERR_L_SEQ_DI4	FORCE_ERR_L_SEQ_DI3	FORCE_ERR_L_SEQ_DI2	FORCE_ERR_L_SEQ_DI1	FORCE_ERR_L_SEQ_DI0
		15:8
		7:0	FORCE_ERR_L_BNDRY_MATCH_DI7	FORCE_ERR_L_BNDRY_MATCH_DI6	FORCE_ERR_L_BNDRY_MATCH_DI5	FORCE_ERR_L_BNDRY_MATCH_DI4	FORCE_ERR_L_BNDRY_MATCH_DI3	FORCE_ERR_L_BNDRY_MATCH_DI2	FORCE_ERR_L_BNDRY_MATCH_DI1	FORCE_ERR_L_BNDRY_MATCH_DI0
0x013C ... 0x02FF	Reserved
0x0300	CSI_SCRAMBLING	31:24
		23:16
		15:8
		7:0								SCRAMBLE_ENABLE
0x0304	CSI_SCRAMBLING_SEED0	31:24
		23:16
		15:8	SCRAMBLE_SEED_LANE0[15:8]
		7:0	SCRAMBLE_SEED_LANE0[7:0]
0x0308	CSI_SCRAMBLING_SEED1	31:24
		23:16
		15:8	SCRAMBLE_SEED_LANE1[15:8]
		7:0	SCRAMBLE_SEED_LANE1[7:0]